IEICE TRANSACTIONS on Information
The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory
Summary :
JUMP-1 is currently under development by seven Japanese universities to establish techniques for building an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. RDT router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme. By using 0.5µm BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock (50MHz). Long coaxial cables (4m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buffers allow to push and pull a flit of the packet simultaneously.
- Publication
- IEICE TRANSACTIONS on Information Vol.E80-D No.9 pp.854-862
- Publication Date
- 1997/09/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Issue on Architectures, Algorithms and Networks for Massively Parallel Computing)
- Category
- Interconnection Networks
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Hiroaki NISHI, Ken-ichiro ANJO, Tomohiro KUDOH, Hideharu AMANO, "The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory" in IEICE TRANSACTIONS on Information,
vol. E80-D, no. 9, pp. 854-862, September 1997, doi: .
Abstract: JUMP-1 is currently under development by seven Japanese universities to establish techniques for building an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. RDT router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme. By using 0.5µm BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock (50MHz). Long coaxial cables (4m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buffers allow to push and pull a flit of the packet simultaneously.
URL: https://global.ieice.org/en_transactions/information/10.1587/e80-d_9_854/_p
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@ARTICLE{e80-d_9_854,
author={Hiroaki NISHI, Ken-ichiro ANJO, Tomohiro KUDOH, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory},
year={1997},
volume={E80-D},
number={9},
pages={854-862},
abstract={JUMP-1 is currently under development by seven Japanese universities to establish techniques for building an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. RDT router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme. By using 0.5µm BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock (50MHz). Long coaxial cables (4m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buffers allow to push and pull a flit of the packet simultaneously.},
keywords={},
doi={},
ISSN={},
month={September},}
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TY - JOUR
TI - The RDT Router Chip: A Versatile Router for Supporting a Distributed Shared Memory
T2 - IEICE TRANSACTIONS on Information
SP - 854
EP - 862
AU - Hiroaki NISHI
AU - Ken-ichiro ANJO
AU - Tomohiro KUDOH
AU - Hideharu AMANO
PY - 1997
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E80-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 1997
AB - JUMP-1 is currently under development by seven Japanese universities to establish techniques for building an efficient distributed shared memory on a massively parallel processor. It provides a coherent cache with reduced hierarchical bit-map directory scheme to achieve cost effective and high performance management. Messages for coherent cache are transferred through a fat tree on the RDT (Recursive Diagonal Torus) interconnection network. RDT router supports versatile functions including multicast and acknowledge combining for the reduced hierarchical bit-map directory scheme. By using 0.5µm BiCMOS SOG technology, it can transfer all packets synchronized with a unique CPU clock (50MHz). Long coaxial cables (4m at maximum) are directly driven with the ECL interface of this chip. Using the dual port RAM, packet buffers allow to push and pull a flit of the packet simultaneously.
ER -
English
