IEICE TRANSACTIONS on Information
Fast Testable Design for SRAM-Based FPGAs
Summary :
This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
- Publication
- IEICE TRANSACTIONS on Information Vol.E83-D No.5 pp.1116-1127
- Publication Date
- 2000/05/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- PAPER
- Category
- Fault Tolerance
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Abderrahim DOUMAR, Toshiaki OHMAMEUDA, Hideo ITO, "Fast Testable Design for SRAM-Based FPGAs" in IEICE TRANSACTIONS on Information,
vol. E83-D, no. 5, pp. 1116-1127, May 2000, doi: .
Abstract: This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
URL: https://global.ieice.org/en_transactions/information/10.1587/e83-d_5_1116/_p
Copy
@ARTICLE{e83-d_5_1116,
author={Abderrahim DOUMAR, Toshiaki OHMAMEUDA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Fast Testable Design for SRAM-Based FPGAs},
year={2000},
volume={E83-D},
number={5},
pages={1116-1127},
abstract={This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.},
keywords={},
doi={},
ISSN={},
month={May},}
Copy
TY - JOUR
TI - Fast Testable Design for SRAM-Based FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 1116
EP - 1127
AU - Abderrahim DOUMAR
AU - Toshiaki OHMAMEUDA
AU - Hideo ITO
PY - 2000
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E83-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2000
AB - This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.
ER -
English
