The capacitance and the resistance of the Au/PrBa2Cu3Oy (PBCO)/YBa2Cu3Ox (YBCO) structure were measured at liquid helium temperature. A film of YBCO was deposited by rf magnetron sputtering at 700, and its thickness was 250 nm. A film of PBCO was deposited by rf magnetron sputtering at 690, and its thickness was less than 375 nm. The inverse capacitance and the resistance of the structure increased with PBCO thickness when PBCO thickness was more than 70 nm. However, the inverse capacitance was near zero, and the resistance was much less than that of PBCO itself when PBCO thickness was less than 70 nm. These results show the possibility that the electric property of PBCO within 70 nm from the PBCO/YBCO interface is different from that of PBCO itself, that is, there is a low-resistance region in PBCO near the YBCO/PBCO interface.

This paper presents a new design for testing SRAM-based field programmable gate arrays (FPGAs). The original FPGA's SRAM memory is modified so that the FPGA may have the facility to loop the testing configuration data inside the chip. The full testing of the FPGA is achieved by loading typically only one carefully chosen testing configuration data instead of the whole configurations data. The other required configurations data are obtained by shifting the first one inside the chip. As a result, the test becomes faster. This method does not need a large off-chip memory for the test. The evaluation results prove that this method is very effective when the complexity of the configurable blocks (CLBs) or the chip size increases.

In this paper, a dynamic constructive algorithm for fault tolerant feedforward neural network, called DCFTA, is proposed. The algorithm starts with a network with single hidden neuron, and a new hidden unit is added dynamically to the network whenever it fails to converge. Before inserting the new hidden neuron into the network, only the weights connecting the new hidden neuron to the other neurons are trained (i. e. , updated) until there is no significant reduction of the output error. To generate a fault tolerant network, the relevance of each synaptic weight is estimated in each cycle, and only the weights which have their relevance less than a specified threshold are updated in that cycle. The loss of a connections between neurons (which are equivalent to stuck-at-0 faults) are assumed. The simulation results indicate that the network constructed by DCFTA has a significant fault tolerance ability.