IEICE TRANSACTIONS on Information
Evaluation and Comparison of Implementation Alternatives for Look-up Tables for Plastic Cell Architecture
Summary :
In this paper, the efficient structure of an LUT (look-up table) for an asynchronous reconfigurable PCA (Plastic Cell Architecture) device is investigated. A total of 15 types of implementation alternatives for LUTs are evaluated and compared in an empirical manner in which full custom layout design is developed and simulated. The evaluation results show that by introducing transmission gates in memory cells in an LUT, read time can be improved by 14.3% at the cost of 13.6% area increase compared to a conventional speed oriented implementation. It is also shown that use of transmission gates reduces 6.4% of area and 19.2% of read time against a conventional area oriented LUT implementation.
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- IEICE TRANSACTIONS on Information Vol.E86-D No.5 pp.850-858
- Publication Date
- 2003/05/01
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- Type of Manuscript
- Special Section PAPER (Special Issue on Reconfigurable Computing)
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Jun'ichiro TAKEMOTO, Toshihiro GOTO, Yuichiro SHIBATA, Kiyoshi OGURI, "Evaluation and Comparison of Implementation Alternatives for Look-up Tables for Plastic Cell Architecture" in IEICE TRANSACTIONS on Information,
vol. E86-D, no. 5, pp. 850-858, May 2003, doi: .
Abstract: In this paper, the efficient structure of an LUT (look-up table) for an asynchronous reconfigurable PCA (Plastic Cell Architecture) device is investigated. A total of 15 types of implementation alternatives for LUTs are evaluated and compared in an empirical manner in which full custom layout design is developed and simulated. The evaluation results show that by introducing transmission gates in memory cells in an LUT, read time can be improved by 14.3% at the cost of 13.6% area increase compared to a conventional speed oriented implementation. It is also shown that use of transmission gates reduces 6.4% of area and 19.2% of read time against a conventional area oriented LUT implementation.
URL: https://global.ieice.org/en_transactions/information/10.1587/e86-d_5_850/_p
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@ARTICLE{e86-d_5_850,
author={Jun'ichiro TAKEMOTO, Toshihiro GOTO, Yuichiro SHIBATA, Kiyoshi OGURI, },
journal={IEICE TRANSACTIONS on Information},
title={Evaluation and Comparison of Implementation Alternatives for Look-up Tables for Plastic Cell Architecture},
year={2003},
volume={E86-D},
number={5},
pages={850-858},
abstract={In this paper, the efficient structure of an LUT (look-up table) for an asynchronous reconfigurable PCA (Plastic Cell Architecture) device is investigated. A total of 15 types of implementation alternatives for LUTs are evaluated and compared in an empirical manner in which full custom layout design is developed and simulated. The evaluation results show that by introducing transmission gates in memory cells in an LUT, read time can be improved by 14.3% at the cost of 13.6% area increase compared to a conventional speed oriented implementation. It is also shown that use of transmission gates reduces 6.4% of area and 19.2% of read time against a conventional area oriented LUT implementation.},
keywords={},
doi={},
ISSN={},
month={May},}
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TY - JOUR
TI - Evaluation and Comparison of Implementation Alternatives for Look-up Tables for Plastic Cell Architecture
T2 - IEICE TRANSACTIONS on Information
SP - 850
EP - 858
AU - Jun'ichiro TAKEMOTO
AU - Toshihiro GOTO
AU - Yuichiro SHIBATA
AU - Kiyoshi OGURI
PY - 2003
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E86-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2003
AB - In this paper, the efficient structure of an LUT (look-up table) for an asynchronous reconfigurable PCA (Plastic Cell Architecture) device is investigated. A total of 15 types of implementation alternatives for LUTs are evaluated and compared in an empirical manner in which full custom layout design is developed and simulated. The evaluation results show that by introducing transmission gates in memory cells in an LUT, read time can be improved by 14.3% at the cost of 13.6% area increase compared to a conventional speed oriented implementation. It is also shown that use of transmission gates reduces 6.4% of area and 19.2% of read time against a conventional area oriented LUT implementation.
ER -
English
