This paper proposes 0-1-A-Ā LUT, a new programmable logic using atom switches, and a delay-optimal mapping algorithm for it. Atom switch is a non-volatile memory device of very small geometry which is fabricated between metal layers of a VLSI, and it can be used as a switch device of very small on-resistance and parasitic capacitance. While considerable area reduction of Look Up Tables (LUTs) used in conventional Field Programmable Gate Arrays (FPGAs) has been achieved by simply replacing each SRAM element with a memory element using a pair of atom switches, our 0-1-A-Ā LUT achieves further area and delay reduction. Unlike the conventional atom-switch-based LUT in which all k input signals are fed to a MUX, one of input signals is fed to the switch array, resulting area reduction due to the reduced number of inputs of the MUX from 2k to 2k-1, as well as delay reduction due to reduced fanout load of the input buffers. Since the fanout of this input buffers depends on the mapped logic function, this paper also proposes technology mapping algorithms to select logic function of fewer number of fanouts of input buffers to achieve further delay reduction. From our experiments, the circuit delay using our k-LUT is 0.94% smaller in the best case compared with using the conventional atom-switch-based k-LUT.

A class-E power amplifier (PA) with novel dynamic biasing scheme is proposed to enhance power added efficiency (PAE) over a wide power range. A look-up table (LUT) adjusts input power and drain supply voltage simultaneously to keep switch mode condition of a power transistor and to optimize the PAE. Experimental results show that the class-E PA using the proposed scheme with harmonic suppression filter gives the PAE higher than 80% over 8.5,dB range with less than 40,dBc harmonic suppression.

This paper presents an efficient approach for logarithmic and anti-logarithmic converters which can be used in the arithmetic unit of hybrid number system processors and logarithm/exponent function generators in DSP applications. By employing the novel quasi-symmetrical difference method with only the simple shift-add logic and the look-up table, the proposed approach can reduce the hardware area and improve the conversion speed significantly while achieve similar accuracy compared with the previous methods. The implementation results in both FPGA and 0.18-µm CMOS technology are also presented and discussed.

Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.

In this paper, we propose a power amplifier linearization technique combined with iterative noise cancelation. This method alleviates the effect of added noises which prevents the predistorter (PD) from estimating the exact characteristics of the power amplifier (PA). To iteratively cancel the noise added in the feedback signal, the output signal of the power amplifier without noise is reconstructed by applying the inverse characteristics of the PD to the predistorted signals. The noise can be revealed by subtracting the reconstructed signals from the feedback signals. Simulation results based on the mean-square error (MSE) and power spectral density (PSD) criteria are presented to evaluate PD performance. The results show that the iterative noise cancelation significantly enhances the MSE performance, which leads to an improvement of the out-of-band power suppression. The performance of the proposed technique is verified by computer simulation and hardware test results.

To improve simulation precision, the signal model of navigation satellite signal simulators is illustrated, and the generation mechanism and evaluation criteria of an important error source-phase jitter in baseband signal generation, are studied subsequently. An improved baseband signal generator based on dual-ROM look-up table structure is designed with the application of a newly-established concept-virtual sampling rate. Pre-storage of typical baseband signal data and sampling rate conversion adaptive to Doppler frequency shifts are adopted to achieve the high-precision simulation of baseband signals. Performance analysis of the proposed baseband signal generator demonstrates that it can successfully suppress phase jitter and has better spectral performance, generating high-precision baseband signals, which paves the way to improving the overall precision of navigation satellite signal simulators.

The photo-mask cost of standard-cell-based ASICs has been increased so prohibitively that low-volume production LSIs are difficult to fabricate due to high non-recurring engineering (NRE) cost including mask cost. Recently, user-programmable devices, such as FPGAs are started to be used for low-volume consumer products. However, FPGAs cannot be replaced for general purpose because of its lower speed-performance and higher power consumption. In this paper, we propose the user-programmable architecture called VPEX (Via Programmable logic device using EXclusive-or array), in which the hardware logic can be programmed by changing layout patterns on 2 via-layers. The logic element (LE) of VPEX consists of complex-gate-type EXclusive OR (EXOR) and Inverter (NOT) gates. The single LE can output 12 logics which include NOT, Buffer (BUF), all 2-inputs logic functions, 3-inputs AOI21 and inverted-output multiplexer (MUXI) by changing via-1 layout pattern. Furthermore, via-1 layout is optimized for high-throughput EB direct writing, so mask-less programming will be realized in VPEX. We compared the performance of area, speed, and power consumption of VPEX with that of standard-cell-based ASICs and FPGAs. As a result, the speed performance of VPEX was much better than FPGAs and about 1.3-1.6 times worse than standard-cells. We believe that the combination of VPEX architecture and EB direct writing is the best solution for low-volume production LSIs.

This letter presents low-complexity digital pulse shaping filter structures of a direct sequence code division multiple access (DS-CDMA) ultra wide-band (UWB) modem transmitter with a ternary spreading code. The proposed finite impulse response (FIR) filter structures using a look-up table (LUT) have the effect of saving the amount of memory by about 50% to 80% in comparison to the conventional FIR filter structures, and consequently are suitable for a high-speed parallel data process.

The N-dimensional (N-D) Hilbert curve is a one-to-one mapping between N-D space and one-dimensional (1-D) space. It is studied actively in the area of digital image processing as a scan technique (Hilbert scan) because of its property of preserving the spatial relationship of the N-D patterns. Currently there exist several Hilbert scan algorithms. However, these algorithms have two strict restrictions in implementation. First, recursive functions are used to generate a Hilbert curve, which makes the algorithms complex and computationally expensive. Second, all the sides of the scanned region must have the same size and the length must be a power of two, which limits the application of the Hilbert scan greatly. Thus in order to remove these constraints and improve the Hilbert scan for general application, a nonrecursive N-D Pseudo-Hilbert scan algorithm based on two look-up tables is proposed in this paper. The merit of the proposed algorithm is that implementation is much easier than the original one while preserving the original characteristics. The experimental results indicate that the Pseudo-Hilbert scan can preserve point neighborhoods as much as possible and take advantage of the high correlation between neighboring lattice points, and it also shows the competitive performance of the Pseudo-Hilbert scan in comparison with other common scan techniques. We believe that this novel scan technique undoubtedly leads to many new applications in those areas can benefit from reducing the dimensionality of the problem.

In this paper, we show that speed and yield of reconfigurable devices can be enhanced by utilizing within-die (WID) delay variations. An LUT Array LSI is fabricated to confirm whether FPGAs have clear WID variations to be utilized. We can measure delay variations by counting the number of LUTs a signal propagates within a certain time. Clear die-to-die (D2D) and WID variations are observed. We propose a variation model from the measurement results. Adequacy of the model is discussed from randomness of the random component. Effect of the speed and yield enhancement is confirmed using the proposed model. Yield increases from 80.0% to 100.0% by optimizing configurations.

The 2-dimensional (2-D) Hilbert curve is a one-to-one mapping between 2-D space and one-dimensional (1-D) space. It is studied actively in the area of digital image processing as a scan technique (Hilbert scan) because of its property of preserving the spacial relationship of the 2-D patterns. Currently there exist several Hilbert scan algorithms. However, these algorithms have two strict restrictions in implementation. First, recursive functions are used to generate a Hilbert curve, which makes the algorithms complex and computationally expensive. Second, both sides of the scanned rectangle must have same size and each size must be a power of two, which limits the application of the Hilbert scan greatly. In this paper, a Pseudo-Hilbert scan algorithm based on two look-up tables is proposed. The proposed method improves the Hilbert scan to be suitable for real-time processing and general application. The simulation indicates that the Pseudo-Hilbert scan can preserve point neighborhoods as much as possible and take advantage of the high correlation between neighboring lattice points. It also shows competitive performance of the Pseudo-Hilbert scan in comparison with other scan techniques.

This paper presents an approach of logic mapping into LUT-Array-Based PLD where Boolean functions in the form of the sum of generalized complex terms (SGCTs) can be mapped directly. While previous mapping approach requires predetermined variable ordering, our approach performs mapping and variable reordering simultaneously. For the purpose, we propose a directed acyclic graph based on the multiple-valued decision diagram (MDD) and an algorithm to construct the graph. Our algorithm generates candidates of SGCT expressions for each node in a bottom-up manner and selects the variables in the current level by evaluating the sizes of SGCT expressions directly. Experimental results show that our approach reduces the number of terms maximum to 71 percent for the MCNC benchmark circuits.

This paper presents a low-power implementation scheme of interpolation FIR filters using distributed arithmetic (DA). The key idea of the proposed scheme involves look-up tables generating only nonnegative values. Thus, the proposed scheme can minimize the dynamic power consumption of interpolation FIR filters using DA without additional hardware. When used for implementing a pulse shaping filter for CDMA2000 mobile stations, the proposed filter not only has almost the same hardware complexity as the conventional one; it also has approximately 43% reduced power consumption.

In this paper, the efficient structure of an LUT (look-up table) for an asynchronous reconfigurable PCA (Plastic Cell Architecture) device is investigated. A total of 15 types of implementation alternatives for LUTs are evaluated and compared in an empirical manner in which full custom layout design is developed and simulated. The evaluation results show that by introducing transmission gates in memory cells in an LUT, read time can be improved by 14.3% at the cost of 13.6% area increase compared to a conventional speed oriented implementation. It is also shown that use of transmission gates reduces 6.4% of area and 19.2% of read time against a conventional area oriented LUT implementation.

This paper presents a new framework for synthesizing look-up table (LUT) networks. Some of the existing LUT network synthesis methods are based on one or two functional (Boolean) decompositions. Our method also uses functional decompositions, but we try to use various decomposition methods, which include algebraic decompositions. Therefore, this method can be thought of as a general framework for synthesizing LUT networks by integrating various decomposition methods. We use a cost database file which is a unique characteristic in our method. We also present comparisons between our method and some well-known LUT network synthesis methods, and evaluate the final results after placement and routing. Although our method is rather heuristic in nature, the experimental results are encouraging.

This paper presents a new efficient method for finding an "optimal" bi-decomposition form of a logic function. A bi-decomposition form of a logic function is the form: f(X) = α(g1(X1), g2(X2)). We call a bi-decomposition form optimal when the total number of variables in X1 and X2 is the smallest among all bi-decomposition forms of f. This meaning of optimal is adequate especially for the synthesis of LUT (Look-Up Table) networks where the number of function inputs is important for the implementation. In our method, we consider only two bi-decomposition forms; (g1 g2) and (g1 g2). We can easily find all the other types of bi-decomposition forms from the above two decomposition forms. Our method efficiently finds one of the existing optimal bi-decomposition forms based on a branch-and-bound algorithm. Moreover, our method can also decompose incompletely specified functions. Experimental results show that we can construct better networks by using optimal bi-decompositions than by using conventional decompositions.

This paper presents a logic synthesis method for look-up table (LUT) based field programmable gate arrays (FPGAs). We determine functions to be mapped to LUTs by functional decomposition for each of single-output functions. To share LUTs among several functions, we use a new Boolean resubstitution technique. Resubstitution is used to determine whether an existing function is useful to realize another function; thus, we can share common functions among two or more functions. The Boolean resubstitution proposed in this paper is customized for an LUT network synthesis because it is based on support minimization for an incompletely specified function. Experimental results show that our synthesis method produces a small size circuit in a practical amount of time.

The Hilbert curve is one of the simplest curves which pass through all points in a space. Many researchers have worked on this curve from the engineering point of view, such as for an expression of two-dimensional patterns, for data compression in an image or in color space, for pseudo color image displays, etc. A computation algorithm of this curve is usually based on a look-up table instead of a recursive algorithm. In such algorithm, a large memory is required for the path look-up table, and the memory size becomes proportional to the image size. In this paper, we present an implementation of a fast sequential algorithm that requires little memory for two and three dimensional Hilbert curves. Our method is based on some rules of quad-tree traversal in two dimensional space, and octtree traversal in three dimensional space. The two dimensional Hilbert curve is similar to the scanning of a DF (Depth First) expression, which is a quad-tree expression of an image. The important feature is that it scans continuously from one quadrant, which is obtained by quad tree splitting, to the next adjacent one in two dimensional space. From this point, if we consider run-lengths of black and white pixels during the scan, the run-lengths of the Hilbert scan tend to be longer than those of the raster scan and the DF expression scanning. We discuss the application to data compression using binary images and three dimensional data.