IEICE TRANSACTIONS on Information
An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors
Summary :
Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.11 pp.2682-2692
- Publication Date
- 2012/11/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.2682
- Type of Manuscript
- PAPER
- Category
- Image Processing and Video Processing
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Se-yong RO, Lin-bo LUO, Jong-wha CHONG, "An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 11, pp. 2682-2692, November 2012, doi: 10.1587/transinf.E95.D.2682.
Abstract: Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.2682/_p
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@ARTICLE{e95-d_11_2682,
author={Se-yong RO, Lin-bo LUO, Jong-wha CHONG, },
journal={IEICE TRANSACTIONS on Information},
title={An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors},
year={2012},
volume={E95-D},
number={11},
pages={2682-2692},
abstract={Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.},
keywords={},
doi={10.1587/transinf.E95.D.2682},
ISSN={1745-1361},
month={November},}
Copy
TY - JOUR
TI - An Improved Look-Up Table-Based FPGA Implementation of Image Warping for CMOS Image Sensors
T2 - IEICE TRANSACTIONS on Information
SP - 2682
EP - 2692
AU - Se-yong RO
AU - Lin-bo LUO
AU - Jong-wha CHONG
PY - 2012
DO - 10.1587/transinf.E95.D.2682
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 11
JA - IEICE TRANSACTIONS on Information
Y1 - November 2012
AB - Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.
ER -
English
