For robust time delay estimation, we propose a new subspace-based algorithm which estimates the phase shift not between the adjacent samples of the dechirped sinusoid but between the dechirped sinusoids in different bands. We analyze the proposed and the conventional method in AWGN channel and verifiy the proposed algorithm through Monte-carlo simulations in AWGN and multi-path channels.

This paper presents the design and simulation of a power efficient 1:4 interpolation FIR filter with partitioned look Up Table (LUT) structure. Using the symmetry of the filter coefficients and the contents of the LUT, the area of the proposed filter is minimized. The two filters share the partitioned LUT and activate the LUT selectively to realize the low power operation. Experimental results suggest that the proposed filter reduces the power consumption by 25% and simultaneously reduces the gate area by 7% compared to the previously proposed single-architecture dual-channel filter.

As the clock skew is one of the major constraints for high speed synchronous ICs, it must be minimized in order to obtain high performance. But clock skew minimization may increase the total wire length; therefore, clock routing is performed within the given skew bound. Clock routing under the specified skew bound can decrease the total wire length. A new efficient algorithm for bounded clock skew routing using link-edge insertion is proposed in this paper. It satisfies the given skew bound and prevents the total wire length from increasing. Not only the total wire length and delay time minimization algorithm using the new merging point relocation method but also the clock skew reduction algorithm using link-edge insertion technique for a pair of nodes whose delay difference is large is proposed. The proposed algorithm constructs a new clock routing topology which is a generalized graph model, while most previous methods use only tree-structured routing topology. A new cost function is designed in order to select two nodes for link-edge addition. Using this cost function, delay difference or clock skew is reduced by connecting two nodes whose delay difference is large and distance is small. Furthermore, routing topology construction and wire sizing algorithm is used to reduce the clock delay. The proposed algorithm is implemented in C programming language. The experimental results show that the total wire length can be reduced under the given skew bound.

In this paper, we propose a hardware architecture of real-time JPEG encoder for 1.4 mega pixels CMOS image sensor SoC which can be applied to mobile communication devices. The proposed architecture has an efficient interface scheme with CMOS image sensor and other peripherals for real-time encoding. The JPEG encoder supports the base-line JPEG mode, and processes motion images of which resolution is up to 1280960 (CCIR601 YCrCb 4:2:2,15 fps) by real-time processing. The JPEG encoder supports 8 types of resolution, and can serve the 4 levels of image quality through quantization matrix. The proposed JPEG encoder can transfer encoded motion pictures and raw image data from CMOS image sensor to external device through USB 2.0 and a compressed still image is stored at external pseudo SRAM through SRAM interface. And proposed core can communicate parameters of encoding type with other host by I2C. The proposed architecture was implemented with VHDL and verified for the functions with Synopsys and Modelsim. The encoder proposed in this paper was fabricated in process of 0.18 µ of Hynix semiconductor Inc.

In this letter, we present a novel timing offset estimation method for chirp-based communication systems which is robust against frequency offset. For robust timing offset estimation, we propose a partial cross-correlation and differential multiplication method using up and down chirp symbols. The performances of the proposed estimator in indoor multipath channel model provided by IEEE 802.15.4a standard are presented in terms of mean-square error (MSE) obtained by computer simulation. The simulation results show that the proposed estimator has a significantly smaller MSE than the conventional estimators.

In lowlight conditions, images taken by phone cameras usually have too much noise, while images taken using a flash have a high signal-noise ratio (SNR) and look unnatural. This paper proposes a novel imaging method using flash/no-flash image pairs. Through transferring the natural tone of the former to the latter, the resulting image has a high SNR and maintains a natural appearance. For realtime implementation, we use two preview images, which are taken with and without flash, to estimate the transformation function in advance. Then we use this function to adjust the tone of the image captured with flash in real time. Thus, the method does not require a frame memory and it is suitable for cell phone cameras.

In this paper, we propose a novel search and selection method for spreading code set of UWB system and apply it to IEEE 802.15.4a IR-UWB system. To find a spreading code with low spectral peak to average ratio (SPAR) and good auto-correlation property, the proposed method searches spreading codes in the frequency domain based on the time-frequency relation of the spreading code. Using evaluation parameters, we selected the code set which had SPAR reduced about 1.1079 dB, Golay merit factor (GMF) improved by 49% and almost the same modified Golay merit factor (MGMF) compared to the code set used as preambles for IR-UWB system.

In this letter, we propose a novel packet detection and symbol timing synchronization algorithm for MB-OFDM UWB system over multi-path channel. To find more reliable and exact symbol timing, we utilize the merits of the auto- and cross-correlation at the same time. The auto-correlator can gather the energy of the received signal which is distorted by multipath fading. And, the cross-correlator can estimate symbol timing to sample level precision. We define the detection and symbol timing metric as the moving sum of autocorrelation of the pre-computed cross-correlated signals over zero pad duration. Simulation results show that the proposed algorithm can detect the presence of a signal with less than -4 dB SNR and find DFT window with at most 0.1 dB SNR reduction upon the receipt of two symbols.

In this letter, we analyze the effect of the size of observed data on the performance of time delay estimation (TDE) in the chirp spread spectrum (CSS) system. By adjusting the size of observed data, we reduce the effect of DC offsets, which would otherwise degrade the performance of TDE based on CSS, and we optimize the performance of TDE in CSS system. Finally, we derive the optimal size of observed data of TDE in CSS system.

A new estimation algorithm of clock drift in symbol duration for high precision ranging, based on multiple symbols of chirp spread spectrum (CSS) is proposed. Since the permissible error of a crystal oscillator in CSS is relatively high given the need to lower device costs, ranging results are perturbed by clock drift. We establish the phenomenon of clock drift in multiple symbols of CSS, and estimate the clock drift in symbol duration based on phase difference between adjacent symbols. The proposed algorithm is analyzed, and verified by Monte Carlo simulations.

In this paper, a novel White-RGB (WRGB) color filter array-based imaging system for cell phone is presented to reduce noise and reproduce color in low illumination. The core process is based on adaptive diagonal color separation to recover color components from a white signal using diagonal reference blocks and location-based color ratio estimation in the luminance space. The experiments, which are compared with the RGB and state-of-the-art WRGB approaches, show that our imaging system performs well for various spatial frequency images and color restoration in low-light environments.

In this letter, a novel imaging method to reduce the hand shake blur of a cell phone camera without using frame memory is proposed. The method improves the captured image in real time through the use of two additional preview images whose parameters can be calculated in advance and stored in a look-up table. The method does not require frame memory, and thus it can significantly reduce the chip size. The scheme is suitable for integration into a low-cost image sensor of a cell phone camera.

In this letter, we suggest two new efficient hardware structures of correlators for packet and frame synchronization of MB-OFDM UWB. In the proposed structure 1, we suggest a hierarchical structure composed of 8 and 16 tap sub-correlators instead of ordinary 128 tap correlators. In the proposed structure 2, we suggest a structure which uses quantized coefficients and simplified multipliers. Results of simulations indicates that the hardware complexities of proposed structures are reduced to about 54% and 31% with minor performance loss, compared with a conventional method.

In this paper, we propose a new code set which has very low spectral peak to average ratio (SPAR) and good correlation properties for DS-UWB. The codes which have low SPAR are suitable for DS-UWB system which operates in UWB (3.110.4 GHz) because they can utilize more power than high SPAR codes can do. And, in order to reduce inter symbol interference (ISI) and inter piconet interferences, the codes which have good auto- and cross-correlation properties must be used. In this paper, we propose three items; (1) a new code generation method which can generate good SPAR and auto-correlation codes, (2) code selection criteria, and (3) a code set, which has been selected according to the proposed selection criteria. The proposed code set has SPAR reduced about 0.22 dB and GMF improved by 30% compared to the previous code set while it is maintaining almost same cross-correlation properties. Each code of the proposed code set, therefore, has gained 1.43 dB SIR on an average compared to that of the previous code set.

In this paper, we propose memory and performance optimized architecture to accelerate the operation speed of adaptive deblocking filter for H.264/JVT/AVC video coding. The proposed deblocking filter executes loading/storing and filtering operations with only 192 cycles for 1 macroblock. Only 244 internal buffers and 3216 internal SRAM are adopted for the buffering operation of deblocking filter with I/O bandwidth of 32 bit. The proposed architecture can process the filtering operation for 1 macroblock with less filtering cycles and lower memory sizes than some conventional approaches of realizing deblocking filter. The efficient hardware architecture is implemented with novel data arrangement, hybrid filter scheduling and minimum number of buffer. The proposed architecture is suitable for low cost and real-time applications, and the real-time decoding with 1080HD (19201088@30 fps) can be easily achieved when working frequency is 70 MHz.

Range estimation based on time of arrival (TOA) is becoming increasingly important with the emergence of location-based applications and next-generation location-aware wireless sensor networks. For radar and positioning systems, chirp signals have primarily been used due to their inborn signal properties for decomposition. Recently, chirp signal has been selected as the baseline standard of ISO/IEC 24730-5 and IEEE 802.15.4a in 2.4GHz, organized for the development of a real-time accurate positioning system. When estimating the TOA of the received signals in multipath channel, the super-resolution algorithms, known as estimation of signal parameters via rotational invariance techniques (ESPRIT), multiple signal classification method (MUSIC) and matrix pencil (MP), are preferred due to their superiority in decomposing the received paths. For the super-resolution algorithm-based TOA estimation of chirp signals, the received chirp signals must be transformed into a sinusoidal form for the super-resolution algorithm. The conventional transformation, the de-chirping technique, changes the received chirp signals to sinusoids so that the super-resolution algorithms can estimate the TOA of the received chirp signals through a frequency estimation of the transformed sinusoids. In practice, the initial timing synchronizer at receiver tries to find the maximum energy point at which the received paths are overlapped maximally. At this time, the conventional de-chirping yields lossy transformed sinusoids for the first arrival path from the received samples synchronized to the maximum energy point. The first arrival path is not involved in the transformed sinusoids with the conventional transformation, leading to performance degradation. However, the proposed energy efficient time-frequency transformation achieves lossless transformation by using the extended reference chirp signals. The proposed transformation is incorporated with MUSIC-based TOA estimation. The effectiveness of the proposed transformation is analyzed and verified. The root mean squared error (RMSE) of the proposed transformation is compared with Cramer-Rao lower bound and those for the conventional algorithms such as super-resolution, ESPRIT and matrix pencil algorithm in multipath channel.

In this paper, we propose an algorithm for contrast enhancement based on Adaptive Histogram Equalization (AHE) to improve image quality. Most histogram-based contrast enhancement methods have problems with excessive or low image contrast enhancement. This results in unnatural output images and the loss of visual information. The proposed method manipulates the slope of the input of the Probability Density Function (PDF) histogram. We also propose a pixel redistribution method using convolution to compensate for excess pixels after the slope modification procedure. Our method adaptively enhances the contrast of the input image and shows good simulation results compared with conventional methods.

In this paper, we present an efficient time-of-arrival (TOA)-based localization method for wireless sensor networks. The goal of a localization system is to accurately estimate the geographic location of a wireless device. In real wireless sensor networks, accurately estimating mobile device location is difficult because of the presence of various errors. Therefore, localization methods have been studied in recent years. In indoor environments, the accuracy of wireless localization systems is affected by non-line-of-sight (NLOS) errors. The presence of NLOS errors degrades the performance of wireless localization systems. In order to effectively estimate the location of the mobile device, NLOS errors should be recognized and mitigated in indoor environments. In the TOA-based ranging method, the distance between the two wireless devices can be computed by multiplying a signal's propagation delay time by the speed of light. TOA-based localization measures the distance between the mobile station (MS) and three or more base stations (BSs). However, each of the NLOS errors of the measured distance between the i-th BS and the MS is different due to dissimilar obstacles in the direct signal path between the two nodes. In order to accurately estimate the location in a TOA-based localization system, an optimized localization algorithm that selects three measured distances with fewer NLOS errors is necessary. We present an efficient TOA-based localization scheme that combines three selected BSs in wireless sensor networks. This localization scheme yields improved localization performance in wireless sensor networks. In this paper, performance tests are performed, and the simulation results are verified through comparisons between various localization methods and the proposed method. As a result, proposed localization scheme using BS selection achieves remarkably better localization performance than the conventional methods. This is verified by experiments in real environments, and demonstrates a performance analysis in NLOS environments. By using BS selection, we will show an efficient and effective TOA-based localization scheme in wireless sensor networks.

Image warping is usually used to perform real-time geometric transformation of the images captured by the CMOS image sensor of video camera. Several existing look-up table (LUT)-based algorithms achieve real-time performance; however, the size of the LUT is still large, and it has to be stored in off-chip memory. To reduce latency and bandwidth due to the use of off-chip memory, this paper proposes an improved LUT (ILUT) scheme that compresses the LUT to the point that it can be stored in on-chip memory. First, a one-step transformation is adopted instead of using several on-line calculation stages. The memory size of the LUT is then reduced by utilizing the similarity of neighbor coordinates, as well as the symmetric characteristic of video camera images. Moreover, an elaborate pipeline hardware structure, cooperating with a novel 25-point interpolation algorithm, is proposed to accelerate the system and reduce further memory usage. The proposed system is implemented by a field-programmable gate array (FPGA)-based platform. Two different examples show that the proposed ILUT achieves real-time performance with small memory usage and low system requirements.