IEICE TRANSACTIONS on Information
Test Sequence Generation for Test Time Reduction of IDDQ Testing
Summary :
In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.
- Publication
- IEICE TRANSACTIONS on Information Vol.E87-D No.3 pp.537-543
- Publication Date
- 2004/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Test and Verification of VLSI)
- Category
- Test Generation and Compaction
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Hiroyuki YOTSUYANAGI, Masaki HASHIZUME, Takeomi TAMESADA, "Test Sequence Generation for Test Time Reduction of IDDQ Testing" in IEICE TRANSACTIONS on Information,
vol. E87-D, no. 3, pp. 537-543, March 2004, doi: .
Abstract: In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.
URL: https://global.ieice.org/en_transactions/information/10.1587/e87-d_3_537/_p
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@ARTICLE{e87-d_3_537,
author={Hiroyuki YOTSUYANAGI, Masaki HASHIZUME, Takeomi TAMESADA, },
journal={IEICE TRANSACTIONS on Information},
title={Test Sequence Generation for Test Time Reduction of IDDQ Testing},
year={2004},
volume={E87-D},
number={3},
pages={537-543},
abstract={In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - Test Sequence Generation for Test Time Reduction of IDDQ Testing
T2 - IEICE TRANSACTIONS on Information
SP - 537
EP - 543
AU - Hiroyuki YOTSUYANAGI
AU - Masaki HASHIZUME
AU - Takeomi TAMESADA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E87-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2004
AB - In this paper, test time reduction for IDDQ testing is discussed. Although IDDQ testing is known to be effective to detect faults in CMOS circuit, test time of IDDQ testing is larger than that of logic testing since supply current is measured after a circuit is in its quiescent state. It is shown by simulation that test time of IDDQ test mostly depends on switching current. A procedure to modify test vectors and a procedure to arrange test vectors are presented for reducing the test time of IDDQ testing. A test sequence is modified such that switching current quickly disappears. The procedure utilizes a unit delay model to estimate the time of the last transition of logic value from L to H in a circuit. Experimental results for benchmark circuits show the effectiveness of the procedure.
ER -
English
