Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ
Summary :
Abnormal IDDQ (Quiescent power supply current) is the signal to indicate the existence of physical damage which includes the between circuit lines. Using this signal, a CAD-based line pairs with bridging fault (LBFs) detection technique has been developed to enhance the manufacturing yield of advanced logic LSI with scaled-down structure and multi-metal layers. The proposed technique progressively narrows the doubtful LBFs down by logic information and layout structure. This technique, quickly handled, is applied to draw down the distribution chart of bridging fault portion on wafer, the feature of which chart is fed back to manufacturing process and layout design.
- Publication
- IEICE TRANSACTIONS on Information Vol.E87-D No.3 pp.557-563
- Publication Date
- 2004/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Test and Verification of VLSI)
- Category
- Fault Detection
Authors
Keyword
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Masaru SANADA, "Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ" in IEICE TRANSACTIONS on Information,
vol. E87-D, no. 3, pp. 557-563, March 2004, doi: .
Abstract: Abnormal IDDQ (Quiescent power supply current) is the signal to indicate the existence of physical damage which includes the between circuit lines. Using this signal, a CAD-based line pairs with bridging fault (LBFs) detection technique has been developed to enhance the manufacturing yield of advanced logic LSI with scaled-down structure and multi-metal layers. The proposed technique progressively narrows the doubtful LBFs down by logic information and layout structure. This technique, quickly handled, is applied to draw down the distribution chart of bridging fault portion on wafer, the feature of which chart is fed back to manufacturing process and layout design.
URL: https://global.ieice.org/en_transactions/information/10.1587/e87-d_3_557/_p
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@ARTICLE{e87-d_3_557,
author={Masaru SANADA, },
journal={IEICE TRANSACTIONS on Information},
title={Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ},
year={2004},
volume={E87-D},
number={3},
pages={557-563},
abstract={Abnormal IDDQ (Quiescent power supply current) is the signal to indicate the existence of physical damage which includes the between circuit lines. Using this signal, a CAD-based line pairs with bridging fault (LBFs) detection technique has been developed to enhance the manufacturing yield of advanced logic LSI with scaled-down structure and multi-metal layers. The proposed technique progressively narrows the doubtful LBFs down by logic information and layout structure. This technique, quickly handled, is applied to draw down the distribution chart of bridging fault portion on wafer, the feature of which chart is fed back to manufacturing process and layout design.},
keywords={},
doi={},
ISSN={},
month={March},}
Copy
TY - JOUR
TI - Layout-Based Detection Technique of Line Pairs with Bridging Fault Using IDDQ
T2 - IEICE TRANSACTIONS on Information
SP - 557
EP - 563
AU - Masaru SANADA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E87-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2004
AB - Abnormal IDDQ (Quiescent power supply current) is the signal to indicate the existence of physical damage which includes the between circuit lines. Using this signal, a CAD-based line pairs with bridging fault (LBFs) detection technique has been developed to enhance the manufacturing yield of advanced logic LSI with scaled-down structure and multi-metal layers. The proposed technique progressively narrows the doubtful LBFs down by logic information and layout structure. This technique, quickly handled, is applied to draw down the distribution chart of bridging fault portion on wafer, the feature of which chart is fed back to manufacturing process and layout design.
ER -
English
