IEICE TRANSACTIONS on Information
A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
Summary :
This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.
- Publication
- IEICE TRANSACTIONS on Information Vol.E87-D No.3 pp.630-636
- Publication Date
- 2004/03/01
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section PAPER (Special Section on Test and Verification of VLSI)
- Category
- Verification
Authors
Keyword
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Kazutoshi KOBAYASHI, Hidetoshi ONODERA, "A Comprehensive Simulation and Test Environment for Prototype VLSI Verification" in IEICE TRANSACTIONS on Information,
vol. E87-D, no. 3, pp. 630-636, March 2004, doi: .
Abstract: This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.
URL: https://global.ieice.org/en_transactions/information/10.1587/e87-d_3_630/_p
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@ARTICLE{e87-d_3_630,
author={Kazutoshi KOBAYASHI, Hidetoshi ONODERA, },
journal={IEICE TRANSACTIONS on Information},
title={A Comprehensive Simulation and Test Environment for Prototype VLSI Verification},
year={2004},
volume={E87-D},
number={3},
pages={630-636},
abstract={This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.},
keywords={},
doi={},
ISSN={},
month={March},}
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TY - JOUR
TI - A Comprehensive Simulation and Test Environment for Prototype VLSI Verification
T2 - IEICE TRANSACTIONS on Information
SP - 630
EP - 636
AU - Kazutoshi KOBAYASHI
AU - Hidetoshi ONODERA
PY - 2004
DO -
JO - IEICE TRANSACTIONS on Information
SN -
VL - E87-D
IS - 3
JA - IEICE TRANSACTIONS on Information
Y1 - March 2004
AB - This paper describes a comprehensive simulation and test environment for prototype LSI verification. We develop a Perl package, ST, for simulation & test of digital circuits. A designer can describe a testbench with the Perl syntax, which can be converted to various kinds of simulators and LSI testers. Parameters such as a target simulator/tester, cycle time and voltage levels can be changed very easily just modifying arguments of subroutines. We also develop DUT boards which consist of a tester-dependent mother board and a package-dependent daughter board. Using ST and the DUT boards, a designer can start verification just after getting fabricated LSIs.
ER -
English
