Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network

Xu BAI; Michitaka KAMEYAMA

doi:10.1587/transinf.2013LOP0006

Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network

Xu BAI, Michitaka KAMEYAMA

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A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the X-net network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network.

Publication: IEICE TRANSACTIONS on Information Vol.E97-D No.9 pp.2278-2285

Publication Date: 2014/09/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2013LOP0006

Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)

Category: VLSI Architecture

Authors

Xu BAI
Tohoku University
Michitaka KAMEYAMA
Tohoku University

Keyword

multiple-valued reconfigurable VLSI, fine-grain reconfigurable VLSI, global tree local X-net network, logic-in-memory architecture

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Xu BAI, Michitaka KAMEYAMA, "Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network" in IEICE TRANSACTIONS on Information, vol. E97-D, no. 9, pp. 2278-2285, September 2014, doi: 10.1587/transinf.2013LOP0006.
Abstract: A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the X-net network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2013LOP0006/_p

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@ARTICLE{e97-d_9_2278,
author={Xu BAI, Michitaka KAMEYAMA, },
journal={IEICE TRANSACTIONS on Information},
title={Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network},
year={2014},
volume={E97-D},
number={9},
pages={2278-2285},
abstract={A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the X-net network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network.},
keywords={},
doi={10.1587/transinf.2013LOP0006},
ISSN={1745-1361},
month={September},}

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TY - JOUR
TI - Multiple-Valued Fine-Grain Reconfigurable VLSI Using a Global Tree Local X-Net Network
T2 - IEICE TRANSACTIONS on Information
SP - 2278
EP - 2285
AU - Xu BAI
AU - Michitaka KAMEYAMA
PY - 2014
DO - 10.1587/transinf.2013LOP0006
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E97-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2014
AB - A global tree local X-net network (GTLX) is introduced to realize high-performance data transfer in a multiple-valued fine-grain reconfigurable VLSI (MVFG-RVLSI). A global pipelined tree network is utilized to realize high-performance long-distance bit-parallel data transfer. Moreover, a logic-in-memory architecture is employed for solving data transfer bottleneck between a block data memory and a cell. A local X-net network is utilized to realize simple interconnections and compact switch blocks for eight-near neighborhood data transfer. Moreover, multiple-valued signaling is utilized to improve the utilization of the X-net network, where two binary data can be transferred from two adjacent cells to one common adjacent cell simultaneously at each “X” intersection. To evaluate the MVFG-RVLSI, a fast Fourier transform (FFT) operation is mapped onto a previous MVFG-RVLSI using only the X-net network and the MVFG-RVLSI using the GTLX. As a result, the computation time, the power consumption and the transistor count of the MVFG-RVLSI using the GTLX are reduced by 25%, 36% and 56%, respectively, in comparison with those of the MVFG-RVLSI using only the X-net network.
ER -