IEICE TRANSACTIONS on Information
A Fast Quantum Computer Simulator Based on Register Reordering
Summary :
Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.
- Publication
- IEICE TRANSACTIONS on Information Vol.E99-D No.2 pp.332-340
- Publication Date
- 2016/02/01
- Publicized
- 2015/11/19
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2015EDP7260
- Type of Manuscript
- PAPER
- Category
- Computer System
Authors
Masaki NAKANISHI
Yamagata University
Miki MATSUYAMA
Yamagata University
Yumi YOKOO
Yamagata University
Keyword
Latest Issue
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Masaki NAKANISHI, Miki MATSUYAMA, Yumi YOKOO, "A Fast Quantum Computer Simulator Based on Register Reordering" in IEICE TRANSACTIONS on Information,
vol. E99-D, no. 2, pp. 332-340, February 2016, doi: 10.1587/transinf.2015EDP7260.
Abstract: Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2015EDP7260/_p
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@ARTICLE{e99-d_2_332,
author={Masaki NAKANISHI, Miki MATSUYAMA, Yumi YOKOO, },
journal={IEICE TRANSACTIONS on Information},
title={A Fast Quantum Computer Simulator Based on Register Reordering},
year={2016},
volume={E99-D},
number={2},
pages={332-340},
abstract={Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.},
keywords={},
doi={10.1587/transinf.2015EDP7260},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - A Fast Quantum Computer Simulator Based on Register Reordering
T2 - IEICE TRANSACTIONS on Information
SP - 332
EP - 340
AU - Masaki NAKANISHI
AU - Miki MATSUYAMA
AU - Yumi YOKOO
PY - 2016
DO - 10.1587/transinf.2015EDP7260
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E99-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2016
AB - Quantum computer simulators play an important role when we evaluate quantum algorithms. Quantum computation can be regarded as parallel computation in some sense, and thus, it is suitable to implement a simulator on hardware that can process a lot of operations in parallel. In this paper, we propose a hardware quantum computer simulator. The proposed simulator is based on the register reordering method that shifts and swaps registers containing probability amplitudes so that the probability amplitudes of target basis states can be quickly selected. This reduces the number of large multiplexers and improves clock frequency. We implement the simulator on an FPGA. Experiments show that the proposed simulator has scalability in terms of the number of quantum bits, and can simulate quantum algorithms faster than software simulators.
ER -
English
