IEICE TRANSACTIONS on Information
Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
Summary :
Soft processors are widely used in FPGA-based embedded computing systems. For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs. Ultrasmall supports a subset of the MIPS-I instruction set architecture and employs an area efficient microarchitecture to reduce the use of FPGA resources. While supporting the original 32-bit ISA, Ultrasmall uses a 2-bit serial ALU for all of its operations. This approach significantly reduces the resource utilization instead of increasing the performance overheads. In addition to these device-independent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs). Optimizations using specific primitives aggressively reduce the number of occupied slices. Our evaluation result shows that Ultrasmall occupies only 84% of the previous small soft processor. In addition to the utilized resource reduction, Ultrasmall achieves 2.9 times higher performance than the previous approach.
- Publication
- IEICE TRANSACTIONS on Information Vol.E98-D No.12 pp.2150-2158
- Publication Date
- 2015/12/01
- Publicized
- 2015/09/15
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2015PAP0022
- Type of Manuscript
- Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
- Category
- Architecture
Authors
Shinya TAKAMAEDA-YAMAZAKI
Nara Institute of Science and Technology
Hiroshi NAKATSUKA
Tokyo Institute of Technology
Yuichiro TANAKA
Tokyo Institute of Technology
Kenji KISE
Tokyo Institute of Technology
Keyword
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Shinya TAKAMAEDA-YAMAZAKI, Hiroshi NAKATSUKA, Yuichiro TANAKA, Kenji KISE, "Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs" in IEICE TRANSACTIONS on Information,
vol. E98-D, no. 12, pp. 2150-2158, December 2015, doi: 10.1587/transinf.2015PAP0022.
Abstract: Soft processors are widely used in FPGA-based embedded computing systems. For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs. Ultrasmall supports a subset of the MIPS-I instruction set architecture and employs an area efficient microarchitecture to reduce the use of FPGA resources. While supporting the original 32-bit ISA, Ultrasmall uses a 2-bit serial ALU for all of its operations. This approach significantly reduces the resource utilization instead of increasing the performance overheads. In addition to these device-independent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs). Optimizations using specific primitives aggressively reduce the number of occupied slices. Our evaluation result shows that Ultrasmall occupies only 84% of the previous small soft processor. In addition to the utilized resource reduction, Ultrasmall achieves 2.9 times higher performance than the previous approach.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2015PAP0022/_p
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@ARTICLE{e98-d_12_2150,
author={Shinya TAKAMAEDA-YAMAZAKI, Hiroshi NAKATSUKA, Yuichiro TANAKA, Kenji KISE, },
journal={IEICE TRANSACTIONS on Information},
title={Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs},
year={2015},
volume={E98-D},
number={12},
pages={2150-2158},
abstract={Soft processors are widely used in FPGA-based embedded computing systems. For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs. Ultrasmall supports a subset of the MIPS-I instruction set architecture and employs an area efficient microarchitecture to reduce the use of FPGA resources. While supporting the original 32-bit ISA, Ultrasmall uses a 2-bit serial ALU for all of its operations. This approach significantly reduces the resource utilization instead of increasing the performance overheads. In addition to these device-independent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs). Optimizations using specific primitives aggressively reduce the number of occupied slices. Our evaluation result shows that Ultrasmall occupies only 84% of the previous small soft processor. In addition to the utilized resource reduction, Ultrasmall achieves 2.9 times higher performance than the previous approach.},
keywords={},
doi={10.1587/transinf.2015PAP0022},
ISSN={1745-1361},
month={December},}
Copy
TY - JOUR
TI - Ultrasmall: A Tiny Soft Processor Architecture with Multi-Bit Serial Datapaths for FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 2150
EP - 2158
AU - Shinya TAKAMAEDA-YAMAZAKI
AU - Hiroshi NAKATSUKA
AU - Yuichiro TANAKA
AU - Kenji KISE
PY - 2015
DO - 10.1587/transinf.2015PAP0022
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E98-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2015
AB - Soft processors are widely used in FPGA-based embedded computing systems. For such purposes, efficiency in resource utilization is as important as high performance. This paper proposes Ultrasmall, a new soft processor architecture for FPGAs. Ultrasmall supports a subset of the MIPS-I instruction set architecture and employs an area efficient microarchitecture to reduce the use of FPGA resources. While supporting the original 32-bit ISA, Ultrasmall uses a 2-bit serial ALU for all of its operations. This approach significantly reduces the resource utilization instead of increasing the performance overheads. In addition to these device-independent optimizations, we applied several device-dependent optimizations for Xilinx Spartan-3E FPGAs using 4-input lookup tables (LUTs). Optimizations using specific primitives aggressively reduce the number of occupied slices. Our evaluation result shows that Ultrasmall occupies only 84% of the previous small soft processor. In addition to the utilized resource reduction, Ultrasmall achieves 2.9 times higher performance than the previous approach.
ER -
English
