IEICE TRANSACTIONS on Information
An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan
Summary :
Due to outsourcing of numerous stages of the IC manufacturing process to different foundries, the security risk, such as hardware Trojan becomes a potential threat. In this paper, we present a layout aware localized hardware Trojan detection method that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified launch-on-capture (LoC) transition delay fault test pattern application technique is proposed so as to maximize the dynamic power consumption of any target region. The new architecture allows activating any target region and keeping others quiet, which reduces total circuit toggling activity. We evaluate our approach on ISCAS89 benchmark and two practical circuits to demonstrate its effectiveness in side-channel analysis.
- Publication
- IEICE TRANSACTIONS on Information Vol.E100-D No.1 pp.130-139
- Publication Date
- 2017/01/01
- Publicized
- 2016/10/20
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2016EDP7246
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Fakir Sharif HOSSAIN
Nara Institute of Science and Technology
Tomokazu YONEDA
Nara Institute of Science and Technology
Michiko INOUE
Nara Institute of Science and Technology
Keyword
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Fakir Sharif HOSSAIN, Tomokazu YONEDA, Michiko INOUE, "An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan" in IEICE TRANSACTIONS on Information,
vol. E100-D, no. 1, pp. 130-139, January 2017, doi: 10.1587/transinf.2016EDP7246.
Abstract: Due to outsourcing of numerous stages of the IC manufacturing process to different foundries, the security risk, such as hardware Trojan becomes a potential threat. In this paper, we present a layout aware localized hardware Trojan detection method that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified launch-on-capture (LoC) transition delay fault test pattern application technique is proposed so as to maximize the dynamic power consumption of any target region. The new architecture allows activating any target region and keeping others quiet, which reduces total circuit toggling activity. We evaluate our approach on ISCAS89 benchmark and two practical circuits to demonstrate its effectiveness in side-channel analysis.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2016EDP7246/_p
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@ARTICLE{e100-d_1_130,
author={Fakir Sharif HOSSAIN, Tomokazu YONEDA, Michiko INOUE, },
journal={IEICE TRANSACTIONS on Information},
title={An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan},
year={2017},
volume={E100-D},
number={1},
pages={130-139},
abstract={Due to outsourcing of numerous stages of the IC manufacturing process to different foundries, the security risk, such as hardware Trojan becomes a potential threat. In this paper, we present a layout aware localized hardware Trojan detection method that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified launch-on-capture (LoC) transition delay fault test pattern application technique is proposed so as to maximize the dynamic power consumption of any target region. The new architecture allows activating any target region and keeping others quiet, which reduces total circuit toggling activity. We evaluate our approach on ISCAS89 benchmark and two practical circuits to demonstrate its effectiveness in side-channel analysis.},
keywords={},
doi={10.1587/transinf.2016EDP7246},
ISSN={1745-1361},
month={January},}
Copy
TY - JOUR
TI - An Effective and Sensitive Scan Segmentation Technique for Detecting Hardware Trojan
T2 - IEICE TRANSACTIONS on Information
SP - 130
EP - 139
AU - Fakir Sharif HOSSAIN
AU - Tomokazu YONEDA
AU - Michiko INOUE
PY - 2017
DO - 10.1587/transinf.2016EDP7246
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 1
JA - IEICE TRANSACTIONS on Information
Y1 - January 2017
AB - Due to outsourcing of numerous stages of the IC manufacturing process to different foundries, the security risk, such as hardware Trojan becomes a potential threat. In this paper, we present a layout aware localized hardware Trojan detection method that magnifies the detection sensitivity for small Trojan in power-based side-channel analysis. A scan segmentation approach with a modified launch-on-capture (LoC) transition delay fault test pattern application technique is proposed so as to maximize the dynamic power consumption of any target region. The new architecture allows activating any target region and keeping others quiet, which reduces total circuit toggling activity. We evaluate our approach on ISCAS89 benchmark and two practical circuits to demonstrate its effectiveness in side-channel analysis.
ER -
English
