The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer

Naohisa FUKASE; Yasuyuki MIURA; Shigeyoshi WATANABE; M.M. HAFIZUR RAHMAN

doi:10.1587/transinf.2017EDP7031

The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer

Naohisa FUKASE, Yasuyuki MIURA, Shigeyoshi WATANABE, M.M. HAFIZUR RAHMAN

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The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.

Publication: IEICE TRANSACTIONS on Information Vol.E100-D No.10 pp.2478-2492

Publication Date: 2017/10/01

Publicized: 2017/06/30

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2017EDP7031

Type of Manuscript: PAPER

Category: Computer System

Authors

Naohisa FUKASE
  Shonan Institute of Technology
Yasuyuki MIURA
  Shonan Institute of Technology
Shigeyoshi WATANABE
  Shonan Institute of Technology
M.M. HAFIZUR RAHMAN
  International Islamic University

Keyword

interconnection network, network-on-chip (NoC), router, multi-port memory

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Naohisa FUKASE, Yasuyuki MIURA, Shigeyoshi WATANABE, M.M. HAFIZUR RAHMAN, "The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer" in IEICE TRANSACTIONS on Information, vol. E100-D, no. 10, pp. 2478-2492, October 2017, doi: 10.1587/transinf.2017EDP7031.
Abstract: The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2017EDP7031/_p

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@ARTICLE{e100-d_10_2478,
author={Naohisa FUKASE, Yasuyuki MIURA, Shigeyoshi WATANABE, M.M. HAFIZUR RAHMAN, },
journal={IEICE TRANSACTIONS on Information},
title={The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer},
year={2017},
volume={E100-D},
number={10},
pages={2478-2492},
abstract={The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.},
keywords={},
doi={10.1587/transinf.2017EDP7031},
ISSN={1745-1361},
month={October},}

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TY - JOUR
TI - The Performance Evaluation of a 3D Torus Network Using Partial Link-Sharing Method in NoC Router Buffer
T2 - IEICE TRANSACTIONS on Information
SP - 2478
EP - 2492
AU - Naohisa FUKASE
AU - Yasuyuki MIURA
AU - Shigeyoshi WATANABE
AU - M.M. HAFIZUR RAHMAN
PY - 2017
DO - 10.1587/transinf.2017EDP7031
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2017
AB - The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.
ER -