The high performance network-on-chip (NoC) router using minimal hardware resources to minimize the layout area is very essential for NoC design. In this paper, we have proposed a memory sharing method of a wormhole routed NoC architecture to alleviate the area overhead of a NoC router. In the proposed method, a memory is shared by multiple physical links by using a multi-port memory. In this paper, we have proposed a partial link-sharing method and evaluated the communication performance using the proposed method. It is revealed that the resulted communication performance by the proposed methods is higher than that of the conventional method, and the progress ratio of the 3D-torus network is higher than that of 2D-torus network. It is shown that the improvement of communication performance using partial link sharing method is achieved with slightly increase of hardware cost.

This letter describes a design methodology for an arithmetic logic unit (ALU) incorporating reconfigurability based on double-gate carbon nanotube field-effect transistors (DG-CNTFETs). The design of a DG-CNTFET with an ambipolar-property-based reconfigurable static logic circuit is simple and straightforward using an ambipolar binary decision diagram (Am-BDD), which represents the cornerstone for the automatic pass transistor logic (PTL) synthesis flows of ambipolar devices. In this work, an ALU with 16 functions is synthesized by the design methodology of a DG-CNTFET-based reconfigurable static logic circuit. Furthermore, it is shown that the proposed ALU is much more flexible and practical than a conventional DG-CNTFET-based reconfigurable ALU.

Hassoune and O'Connor proposed a dynamically reconfigurable dynamic logic circuit (DRDLC) that generates Boolean functions by using double-gate (DG) carbon nanotube (CNT) FETs, which have an ambipolar property. O'Connor et al. proposed a DRDLC that generates 14 Boolean functions asing two Boolean inputs with seven transistors. Furthermore, DRDLCs that generates all 16 Boolean functions have been proposed. In this paper, we focus on the design of a dynamic logic circuit with n Boolean inputs. First, we show a DRDLC that generates the monomial Boolean functions. Next, we propose a DRDLC that generates the whole set of Boolean functions consisting of t terms or less. Finally, we report the number of Boolean functions generated by the proposed DRDLC.