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IEICE TRANSACTIONS on Information

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Ryuta KAWANO, Hiroshi NAKAHARA, Ikki FUJIWARA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO

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Summary :

End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.

Publication
IEICE TRANSACTIONS on Information Vol.E100-D No.12 pp.2796-2807
Publication Date
2017/12/01
Publicized
2017/07/14
Online ISSN
1745-1361
DOI
10.1587/transinf.2017PAP0019
Type of Manuscript
Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)
Category
Interconnection networks

Authors

Ryuta KAWANO
  Keio University
Hiroshi NAKAHARA
  Keio University
Ikki FUJIWARA
  National Institute of Information and Communications Technology
Hiroki MATSUTANI
  Keio University
Michihiro KOIBUCHI
  National Institute of Informatics
Hideharu AMANO
  Keio University

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