A Layout-Oriented Routing Method for Low-Latency HPC Networks

Ryuta KAWANO; Hiroshi NAKAHARA; Ikki FUJIWARA; Hiroki MATSUTANI; Michihiro KOIBUCHI; Hideharu AMANO

doi:10.1587/transinf.2017PAP0019

A Layout-Oriented Routing Method for Low-Latency HPC Networks

Ryuta KAWANO, Hiroshi NAKAHARA, Ikki FUJIWARA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO

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Summary :

End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.

Publication: IEICE TRANSACTIONS on Information Vol.E100-D No.12 pp.2796-2807

Publication Date: 2017/12/01

Publicized: 2017/07/14

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2017PAP0019

Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)

Category: Interconnection networks

Authors

Ryuta KAWANO
  Keio University
Hiroshi NAKAHARA
  Keio University
Ikki FUJIWARA
  National Institute of Information and Communications Technology
Hiroki MATSUTANI
  Keio University
Michihiro KOIBUCHI
  National Institute of Informatics
Hideharu AMANO
  Keio University

Keyword

high performance computing, network topology, interconnection networks

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Ryuta KAWANO, Hiroshi NAKAHARA, Ikki FUJIWARA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, "A Layout-Oriented Routing Method for Low-Latency HPC Networks" in IEICE TRANSACTIONS on Information, vol. E100-D, no. 12, pp. 2796-2807, December 2017, doi: 10.1587/transinf.2017PAP0019.
Abstract: End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2017PAP0019/_p

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@ARTICLE{e100-d_12_2796,
author={Ryuta KAWANO, Hiroshi NAKAHARA, Ikki FUJIWARA, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Layout-Oriented Routing Method for Low-Latency HPC Networks},
year={2017},
volume={E100-D},
number={12},
pages={2796-2807},
abstract={End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.},
keywords={},
doi={10.1587/transinf.2017PAP0019},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - A Layout-Oriented Routing Method for Low-Latency HPC Networks
T2 - IEICE TRANSACTIONS on Information
SP - 2796
EP - 2807
AU - Ryuta KAWANO
AU - Hiroshi NAKAHARA
AU - Ikki FUJIWARA
AU - Hiroki MATSUTANI
AU - Michihiro KOIBUCHI
AU - Hideharu AMANO
PY - 2017
DO - 10.1587/transinf.2017PAP0019
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E100-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2017
AB - End-to-end network latency has become an important issue for parallel application on large-scale high performance computing (HPC) systems. It has been reported that randomly-connected inter-switch networks can lower the end-to-end network latency. This latency reduction is established in exchange for a large amount of routing information. That is, minimal routing on irregular networks is achieved by using routing tables for all destinations in the networks. In this work, a novel distributed routing method called LOREN (Layout-Oriented Routing with Entries for Neighbors) to achieve low-latency with a small routing table is proposed for irregular networks whose link length is limited. The routing tables contain both physically and topologically nearby neighbor nodes to ensure livelock-freedom and a small number of hops between nodes. Experimental results show that LOREN reduces the average latencies by 5.8% and improves the network throughput by up to 62% compared with a conventional compact routing method. Moreover, the number of required routing table entries is reduced by up to 91%, which improves scalability and flexibility for implementation.
ER -