IEICE TRANSACTIONS on Information
Complete Double Node Upset Tolerant Latch Using C-Element
Summary :
The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.
- Publication
- IEICE TRANSACTIONS on Information Vol.E103-D No.10 pp.2125-2132
- Publication Date
- 2020/10/01
- Publicized
- 2020/06/25
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2020EDP7103
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Yuta YAMAMOTO
Chiba University
Kazuteru NAMBA
Chiba University
Keyword
Latest Issue
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Yuta YAMAMOTO, Kazuteru NAMBA, "Complete Double Node Upset Tolerant Latch Using C-Element" in IEICE TRANSACTIONS on Information,
vol. E103-D, no. 10, pp. 2125-2132, October 2020, doi: 10.1587/transinf.2020EDP7103.
Abstract: The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020EDP7103/_p
Copy
@ARTICLE{e103-d_10_2125,
author={Yuta YAMAMOTO, Kazuteru NAMBA, },
journal={IEICE TRANSACTIONS on Information},
title={Complete Double Node Upset Tolerant Latch Using C-Element},
year={2020},
volume={E103-D},
number={10},
pages={2125-2132},
abstract={The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.},
keywords={},
doi={10.1587/transinf.2020EDP7103},
ISSN={1745-1361},
month={October},}
Copy
TY - JOUR
TI - Complete Double Node Upset Tolerant Latch Using C-Element
T2 - IEICE TRANSACTIONS on Information
SP - 2125
EP - 2132
AU - Yuta YAMAMOTO
AU - Kazuteru NAMBA
PY - 2020
DO - 10.1587/transinf.2020EDP7103
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E103-D
IS - 10
JA - IEICE TRANSACTIONS on Information
Y1 - October 2020
AB - The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.
ER -
English
