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Complete Double Node Upset Tolerant Latch Using C-Element

Yuta YAMAMOTO, Kazuteru NAMBA

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Summary :

The recent development of semiconductor technology has led to downsized, large-scaled and low-power VLSI systems. However, the incidence of soft errors has increased. Soft errors are temporary events caused by striking of α-rays and high energy neutron radiation. Since the scale of VLSI has become smaller in recent development, it is necessary to consider the occurrence of not only single node upset (SNU) but also double node upset (DNU). The existing High-performance, Low-cost, and DNU Tolerant Latch design (HLDTL) does not completely tolerate DNU. This paper presents a new design of a DNU tolerant latch to resolve this issue by adding some transistors to the HLDTL latch.

Publication
IEICE TRANSACTIONS on Information Vol.E103-D No.10 pp.2125-2132
Publication Date
2020/10/01
Publicized
2020/06/25
Online ISSN
1745-1361
DOI
10.1587/transinf.2020EDP7103
Type of Manuscript
PAPER
Category
Dependable Computing

Authors

Yuta YAMAMOTO
  Chiba University
Kazuteru NAMBA
  Chiba University

Keyword