IEICE TRANSACTIONS on Information
The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit
Summary :
This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.
- Publication
- IEICE TRANSACTIONS on Information Vol.E104-D No.8 pp.1146-1153
- Publication Date
- 2021/08/01
- Publicized
- 2021/04/01
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.2020LOP0008
- Type of Manuscript
- Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)
- Category
- Circuit Technologies
Authors
Ryoichi MIYAUCHI
Tokyo University of Science
Akio YOSHIDA
ROHM Co., Ltd.
Shuya NAKANO
University of Miyazaki
Hiroki TAMURA
University of Miyazaki
Koichi TANNO
University of Miyazaki
Yutaka FUKUCHI
Tokyo University of Science
Yukio KAWAMURA
LAPIS Semiconductor Co., Ltd.
Yuki KODAMA
LAPIS Semiconductor Co., Ltd.
Yuichi SEKIYA
LAPIS Semiconductor Co., Ltd.
Keyword
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Ryoichi MIYAUCHI, Akio YOSHIDA, Shuya NAKANO, Hiroki TAMURA, Koichi TANNO, Yutaka FUKUCHI, Yukio KAWAMURA, Yuki KODAMA, Yuichi SEKIYA, "The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit" in IEICE TRANSACTIONS on Information,
vol. E104-D, no. 8, pp. 1146-1153, August 2021, doi: 10.1587/transinf.2020LOP0008.
Abstract: This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020LOP0008/_p
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@ARTICLE{e104-d_8_1146,
author={Ryoichi MIYAUCHI, Akio YOSHIDA, Shuya NAKANO, Hiroki TAMURA, Koichi TANNO, Yutaka FUKUCHI, Yukio KAWAMURA, Yuki KODAMA, Yuichi SEKIYA, },
journal={IEICE TRANSACTIONS on Information},
title={The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit},
year={2021},
volume={E104-D},
number={8},
pages={1146-1153},
abstract={This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.},
keywords={},
doi={10.1587/transinf.2020LOP0008},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - The Fractional-N All Digital Frequency Locked Loop with Robustness for PVT Variation and Its Application for the Microcontroller Unit
T2 - IEICE TRANSACTIONS on Information
SP - 1146
EP - 1153
AU - Ryoichi MIYAUCHI
AU - Akio YOSHIDA
AU - Shuya NAKANO
AU - Hiroki TAMURA
AU - Koichi TANNO
AU - Yutaka FUKUCHI
AU - Yukio KAWAMURA
AU - Yuki KODAMA
AU - Yuichi SEKIYA
PY - 2021
DO - 10.1587/transinf.2020LOP0008
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E104-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2021
AB - This paper describes the Fractional-N All Digital Frequency Locked Loop (ADFLL) with Robustness for PVT variation and its application for the microcontroller unit. The conventional FLL is difficult to achieve the required specification by using the fine CMOS process. Especially, the conventional FLL has some problems such as unexpected operation and long lock time that are caused by PVT variation. To overcome these problems, we propose a new ADFLL which uses dynamic selecting digital filter coefficients. The proposed ADFLL was evaluatied through the HSPICE simulation and fabricating chips using a 0.13 µm CMOS process. From these results, we observed the proposed ADFLL has robustness for PVT variation by using dynamic selecting digital filter coefficient, and the lock time is improved up to 57%, clock jitter is 0.85 nsec.
ER -
English
