RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining

Hiromu MIYAZAKI; Takuto KANAMORI; Md Ashraful ISLAM; Kenji KISE

doi:10.1587/transinf.2020PAP0015

IEICE TRANSACTIONS on Information

RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining

Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE

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RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.

Publication: IEICE TRANSACTIONS on Information Vol.E103-D No.12 pp.2494-2503

Publication Date: 2020/12/01

Publicized: 2020/09/07

Online ISSN: 1745-1361

DOI: 10.1587/transinf.2020PAP0015

Type of Manuscript: Special Section PAPER (Special Section on Parallel, Distributed, and Reconfigurable Computing, and Networking)

Category: Computer System

Authors

Hiromu MIYAZAKI
  Tokyo Institute of Technology
Takuto KANAMORI
  Tokyo Institute of Technology
Md Ashraful ISLAM
  Tokyo Institute of Technology
Kenji KISE
  Tokyo Institute of Technology

Keyword

soft processor, FPGA, RISC-V, RV32I, Verilog HDL, five-stage pipelining

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Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, "RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining" in IEICE TRANSACTIONS on Information, vol. E103-D, no. 12, pp. 2494-2503, December 2020, doi: 10.1587/transinf.2020PAP0015.
Abstract: RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.2020PAP0015/_p

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@ARTICLE{e103-d_12_2494,
author={Hiromu MIYAZAKI, Takuto KANAMORI, Md Ashraful ISLAM, Kenji KISE, },
journal={IEICE TRANSACTIONS on Information},
title={RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining},
year={2020},
volume={E103-D},
number={12},
pages={2494-2503},
abstract={RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.},
keywords={},
doi={10.1587/transinf.2020PAP0015},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - RVCoreP: An Optimized RISC-V Soft Processor of Five-Stage Pipelining
T2 - IEICE TRANSACTIONS on Information
SP - 2494
EP - 2503
AU - Hiromu MIYAZAKI
AU - Takuto KANAMORI
AU - Md Ashraful ISLAM
AU - Kenji KISE
PY - 2020
DO - 10.1587/transinf.2020PAP0015
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E103-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2020
AB - RISC-V is a RISC based open and loyalty free instruction set architecture which has been developed since 2010, and can be used for cost-effective soft processors on FPGAs. The basic 32-bit integer instruction set in RISC-V is defined as RV32I, which is sufficient to support the operating system environment and suits for embedded systems. In this paper, we propose an optimized RV32I soft processor named RVCoreP adopting five-stage pipelining. Three effective methods are applied to the processor to improve the operating frequency. These methods are instruction fetch unit optimization, ALU optimization, and data memory optimization. We implement RVCoreP in Verilog HDL and verify the behavior using Verilog simulation and an actual Xilinx Atrix-7 FPGA board. We evaluate IPC (instructions per cycle), operating frequency, hardware resource utilization, and processor performance. From the evaluation results, we show that RVCoreP achieves 30.0% performance improvement compared with VexRiscv, which is a high-performance and open source RV32I processor selected from some related works.
ER -

IEICE TRANSACTIONS on Information