Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
Summary :
This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
- Publication
- IEICE TRANSACTIONS on Information Vol.E92-D No.2 pp.269-282
- Publication Date
- 2009/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E92.D.269
- Type of Manuscript
- PAPER
- Category
- Dependable Computing
Authors
Keyword
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Kazuteru NAMBA, Hideo ITO, "Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 2, pp. 269-282, February 2009, doi: 10.1587/transinf.E92.D.269.
Abstract: This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.269/_p
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@ARTICLE{e92-d_2_269,
author={Kazuteru NAMBA, Hideo ITO, },
journal={IEICE TRANSACTIONS on Information},
title={Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding},
year={2009},
volume={E92-D},
number={2},
pages={269-282},
abstract={This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).},
keywords={},
doi={10.1587/transinf.E92.D.269},
ISSN={1745-1361},
month={February},}
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TY - JOUR
TI - Test Compression for Robust Testable Path Delay Fault Testing Using Interleaving and Statistical Coding
T2 - IEICE TRANSACTIONS on Information
SP - 269
EP - 282
AU - Kazuteru NAMBA
AU - Hideo ITO
PY - 2009
DO - 10.1587/transinf.E92.D.269
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2009
AB - This paper proposes a method providing efficient test compression. The proposed method is for robust testable path delay fault testing with scan design facilitating two-pattern testing. In the proposed method, test data are interleaved before test compression using statistical coding. This paper also presents test architecture for two-pattern testing using the proposed method. The proposed method is experimentally evaluated from several viewpoints such as compression rates, test application time and area overhead. For robust testable path delay fault testing on 11 out of 20 ISCAS89 benchmark circuits, the proposed method provides better compression rates than the existing methods such as Huffman coding, run-length coding, Golomb coding, frequency-directed run-length (FDR) coding and variable-length input Huffman coding (VIHC).
ER -
English
