IEICE TRANSACTIONS on Information
A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
Summary :
The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.
- Publication
- IEICE TRANSACTIONS on Information Vol.E92-D No.4 pp.575-583
- Publication Date
- 2009/04/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E92.D.575
- Type of Manuscript
- PAPER
- Category
- VLSI Systems
Authors
Keyword
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Daihan WANG, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, "A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs" in IEICE TRANSACTIONS on Information,
vol. E92-D, no. 4, pp. 575-583, April 2009, doi: 10.1587/transinf.E92.D.575.
Abstract: The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E92.D.575/_p
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@ARTICLE{e92-d_4_575,
author={Daihan WANG, Hiroki MATSUTANI, Michihiro KOIBUCHI, Hideharu AMANO, },
journal={IEICE TRANSACTIONS on Information},
title={A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs},
year={2009},
volume={E92-D},
number={4},
pages={575-583},
abstract={The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.},
keywords={},
doi={10.1587/transinf.E92.D.575},
ISSN={1745-1361},
month={April},}
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TY - JOUR
TI - A Link Removal Methodology for Application-Specific Networks-on-Chip on FPGAs
T2 - IEICE TRANSACTIONS on Information
SP - 575
EP - 583
AU - Daihan WANG
AU - Hiroki MATSUTANI
AU - Michihiro KOIBUCHI
AU - Hideharu AMANO
PY - 2009
DO - 10.1587/transinf.E92.D.575
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E92-D
IS - 4
JA - IEICE TRANSACTIONS on Information
Y1 - April 2009
AB - The regular 2-D mesh topology has been utilized for most of Network-on-Chips (NoCs) on FPGAs. Spatially biased traffic generated in some applications makes a customization method for removing links more efficient, since some links become low utilization. In this paper, a link removal strategy that customizes the router in NoC is proposed for reconfigurable systems in order to minimize the required hardware amount. Based on the pre-analyzed traffic information, links on which the communication amount is small are removed to reduce the hardware cost while maintaining adequate performance. Two policies are proposed to avoid deadlocks and they outperform up*/down* routing, which is a representative deadlock-free routing on irregular topology. In the case of the image recognition application susan, the proposed method can save 30% of the hardware amount without performance degradation.
ER -
English
