HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms

Liang-Bi CHEN; Jiun-Cheng JU; Chien-Chou WANG; Ing-Jer HUANG

doi:10.1587/transinf.E93.D.2100

HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms

Liang-Bi CHEN, Jiun-Cheng JU, Chien-Chou WANG, Ing-Jer HUANG

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Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.

Publication: IEICE TRANSACTIONS on Information Vol.E93-D No.8 pp.2100-2108

Publication Date: 2010/08/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E93.D.2100

Type of Manuscript: Special Section PAPER (Special Section on Multiple-Valued Logic and VLSI Computing)

Category: Multiple-Valued VLSI Technology

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Liang-Bi CHEN, Jiun-Cheng JU, Chien-Chou WANG, Ing-Jer HUANG, "HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms" in IEICE TRANSACTIONS on Information, vol. E93-D, no. 8, pp. 2100-2108, August 2010, doi: 10.1587/transinf.E93.D.2100.
Abstract: Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.2100/_p

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@ARTICLE{e93-d_8_2100,
author={Liang-Bi CHEN, Jiun-Cheng JU, Chien-Chou WANG, Ing-Jer HUANG, },
journal={IEICE TRANSACTIONS on Information},
title={HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms},
year={2010},
volume={E93-D},
number={8},
pages={2100-2108},
abstract={Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.},
keywords={},
doi={10.1587/transinf.E93.D.2100},
ISSN={1745-1361},
month={August},}

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TY - JOUR
TI - HPChecker: An AMBA AHB On-Chip Bus Protocol Checker with Efficient Verification Mechanisms
T2 - IEICE TRANSACTIONS on Information
SP - 2100
EP - 2108
AU - Liang-Bi CHEN
AU - Jiun-Cheng JU
AU - Chien-Chou WANG
AU - Ing-Jer HUANG
PY - 2010
DO - 10.1587/transinf.E93.D.2100
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2010
AB - Bus-based system-on-a-chip (SoC) design has become the major integrated methodology for shortening SoC design time. The main challenge is how to verify on-chip bus protocols efficiently. Although traditional simulation-based bus protocol monitors can check whether bus signals obey bus protocol or not. They are still lack of an efficient bus protocols verification environment such as FPGA-level or chip-level. To overcome the shortage, we propose a rule-based synthesizable AMBA AHB on-chip bus protocol checker, which contains 73 related AHB on-chip bus protocol rules to check AHB bus signal behaviors, and two corresponding verification mechanisms: an error reference table (ERT) and a windowed trace buffer, to shorten verification time.
ER -