Parallel DFA Architecture for Ultra High Throughput DFA-Based Pattern Matching

Yi TANG; Junchen JIANG; Xiaofei WANG; Chengchen HU; Bin LIU; Zhijia CHEN

doi:10.1587/transinf.E93.D.3232

Parallel DFA Architecture for Ultra High Throughput DFA-Based Pattern Matching

Yi TANG, Junchen JIANG, Xiaofei WANG, Chengchen HU, Bin LIU, Zhijia CHEN

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Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

Publication: IEICE TRANSACTIONS on Information Vol.E93-D No.12 pp.3232-3242

Publication Date: 2010/12/01

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Online ISSN: 1745-1361

DOI: 10.1587/transinf.E93.D.3232

Type of Manuscript: Special Section PAPER (Special Section on Parallel and Distributed Computing and Networking)

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Yi TANG, Junchen JIANG, Xiaofei WANG, Chengchen HU, Bin LIU, Zhijia CHEN, "Parallel DFA Architecture for Ultra High Throughput DFA-Based Pattern Matching" in IEICE TRANSACTIONS on Information, vol. E93-D, no. 12, pp. 3232-3242, December 2010, doi: 10.1587/transinf.E93.D.3232.
Abstract: Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E93.D.3232/_p

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@ARTICLE{e93-d_12_3232,
author={Yi TANG, Junchen JIANG, Xiaofei WANG, Chengchen HU, Bin LIU, Zhijia CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={Parallel DFA Architecture for Ultra High Throughput DFA-Based Pattern Matching},
year={2010},
volume={E93-D},
number={12},
pages={3232-3242},
abstract={Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.},
keywords={},
doi={10.1587/transinf.E93.D.3232},
ISSN={1745-1361},
month={December},}

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TY - JOUR
TI - Parallel DFA Architecture for Ultra High Throughput DFA-Based Pattern Matching
T2 - IEICE TRANSACTIONS on Information
SP - 3232
EP - 3242
AU - Yi TANG
AU - Junchen JIANG
AU - Xiaofei WANG
AU - Chengchen HU
AU - Bin LIU
AU - Zhijia CHEN
PY - 2010
DO - 10.1587/transinf.E93.D.3232
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E93-D
IS - 12
JA - IEICE TRANSACTIONS on Information
Y1 - December 2010
AB - Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.
ER -