This paper introduces an unsupervised method for motion pattern learning and abnormality detection from video surveillance. In the preprocessing steps, trajectories are segmented based on their locations, and the sub-trajectories are represented as codebooks. Under our framework, Hidden Markov Models (HMMs) are used to characterize the motion pattern feature of the trajectory groups. The state of trajectory is represented by a HMM and has a probability distribution over the possible output sub-trajectories. Bayesian Information Criterion (BIC) is introduced to measure the similarity between groups. Based on the pairwise similarity scores, an affinity matrix is constructed which indicates the distance between different trajectory groups. An Adaptable Dynamic Hierarchical Clustering (ADHC) tree is proposed to gradually merge the most similar groups and form the trajectory motion patterns, which implements a simpler and more tractable dynamical clustering procedure in updating the clustering results with lower time complexity and avoids the traditional overfitting problem. By using the HMM models generated for the obtained trajectory motion patterns, we may recognize motion patterns and detect anomalies by computing the likelihood of the given trajectory, where a maximum likelihood for HMM indicates a pattern, and a small one below a threshold suggests an anomaly. Experiments are performed on EIFPD trajectory datasets from a structureless scene, where pedestrians choose their walking paths randomly. The experimental results show that our method can accurately learn motion patterns and detect anomalies with better performance.

Multi-pattern matching is a key technique for implementing network security applications such as Network Intrusion Detection/Protection Systems (NIDS/NIPSes) where every packet is inspected against tens of thousands of predefined attack signatures written in regular expressions (regexes). To this end, Deterministic Finite Automaton (DFA) is widely used for multi-regex matching, but existing DFA-based researches have claimed high throughput at an expense of extremely high memory cost, so fail to be employed in devices such as high-speed routers and embedded systems where the available memory is quite limited. In this paper, we propose a parallel architecture of DFA called Parallel DFA (PDFA) taking advantage of the large amount of concurrent flows to increase the throughput with nearly no extra memory cost. The basic idea is to selectively store the underlying DFA in memory modules that can be accessed in parallel. To explore its potential parallelism we intensively study DFA-split schemes from both state and transition points in this paper. The performance of our approach in both the average cases and the worst cases is analyzed, optimized and evaluated by numerical results. The evaluation shows that we obtain an average speedup of 100 times compared with traditional DFA-based matching approach.

This paper studies the optimization of the effective channel capacity of wideband code division multiple access (WCDMA) systems under Rayleigh fading environments. Firstly, the results for Shannon capacity of fading channels with channel side information are reviewed, where the capacity is achieved by using an optimal power control scheme. Secondly, an optimal interference threshold is set for a given system outage probability Pout to minimize total interference. Finally, the effective channel capacity of WCDMA is defined and a target SIR level γ* is derived with the Lagrangian multiplier method to maximize the effective channel capacity. It is shown that is dependent on the power control interference ratio (PCIR) ρ, the number of diversity paths identified by the receiver M, and the outage probability of the system. Simulation results are provided to validate the theoretical deductions. We conclude that the total effective channel capacity will be maximized as long as M4, and ρ0.5 for a proper value of .

As the track becomes narrower, the effects of track edge become more significant. These effects, such as the amplitude reduction, variations in the shape of the isolated pulse, the partial erasure and the amplitude asymmetry, are dependent on head/disk combination and the off-track position. These relationships are discussed in detail in this paper. More importantly, an off-track model is proposed to study the off-track BER performance for the head with narrow track width. The BER performances of EPRML channel for different off-track cases and different head/media combinations are studied based on this model. Simulation results have proved that this model is a useful tool for simulation of system performance.

This paper discusses the relationships of two important program classes of linearly recursive programs, that is, decomposable programs and rule commutative programs. We prove that the decomposable programs are always rule commutative. Furthermore, the rule commutative programs that satisfy certain conditions are decomposable. These results are meaningful for integrating the related specified optimization algorithms.

In VDSM era, crosstalk is becoming a more and more vital factor in high performance VLSI designs, making noise mitigation in early design stages necessary. In this paper, we propose an effective algorithm optimizing crosstalk under congestion constraint in the layer assignment stage. A new model for noise severity measurement is developed where wire length is used as a scale for the noise immunity, and both capacitive and inductive coupling between sensitive nets are considered. We also take shield insertion into account for further crosstalk mitigation. Experimental results show that our approach could efficiently reduce crosstalk noise without compromising congestion compared to the algorithm proposed in [1].

The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.