High temperature adversely impacts on circuit's reliability, performance, and leakage power. During behavioral synthesis, both resource usage allocation and resource binding influence thermal profile. Current thermal-aware behavioral syntheses do not utilize location information of resources from floorplan and in addition only focus on binding, ignoring allocation. This paper proposes thermal-aware behavioral synthesis with resource usage allocation. Based on a hybrid metric of physical location information and temperature, we rebind operations and reallocate the number of resources under area constraint. Our approach effectively controls peak temperature and creates even power densities among resources of different types and within resources of the same type. Experimental results show an average of 8.6 drop in peak temperature and 5.3% saving of total power consumption with little latency overhead.

In VDSM era, crosstalk is becoming a more and more vital factor in high performance VLSI designs, making noise mitigation in early design stages necessary. In this paper, we propose an effective algorithm optimizing crosstalk under congestion constraint in the layer assignment stage. A new model for noise severity measurement is developed where wire length is used as a scale for the noise immunity, and both capacitive and inductive coupling between sensitive nets are considered. We also take shield insertion into account for further crosstalk mitigation. Experimental results show that our approach could efficiently reduce crosstalk noise without compromising congestion compared to the algorithm proposed in [1].

Based on the minimum mean square error (MMSE) detection with iterative soft interference cancellation (SoIC), we propose an adaptive MMSE (A-MMSE) algorithm which acts as an MMSE operator at the beginning of iteration and a maximum ratio combination (MRC) when the interference is nearly cancelled. In our algorithm, a modified metric matrix based on the reliability of soft information from the decoder output is multiplied by the interference part of channel correlation matrix to update the detection operator. The simulation results have shown that this A-MMSE iterative SoIC algorithm can achieve significant performance advantage over the traditional MMSE iterative SoIC algorithm.

The voltage island style has been widely accepted as an effective way to design low power high performance chips. This paper proposes an automated voltage island generation flow in standard cell based designs. Two important objectives in voltage island designs are addressed in this flow: 1) reducing power dissipation under given performance constraints; 2) reducing implementation overheads, mainly layout overheads caused by cell clustering to form islands. The first objective is handled with timing and power driven netweighting and timing analysis in voltage assignment. For the second objective, we propose layout aware voltage assignment, i.e., voltage assignment during placement. We iteratively perform the following to adjustments: adjustment on voltage assignment to facilitate voltage island generation, and adjustment on cell locations to cluster cells in voltage islands. These iterations lead to a flow featured with tightly integrated voltage assignment and cell placement. Experimental results have demonstrated the advantages of our approach.

This paper presents a novel approach to reducing the complexity of the transient linear circuit analysis for a hybrid structured clock network. Topology reduction is first used to reduce the complexity of the circuits and a preconditioned Krylov-subspace iterative method is then used to perform the nodal analysis on the reduced circuits. By proper selection of the simulation time step and interval based on Elmore delays, the delay of the clock signal between the clock source and the sink node as well as the clock skews between the sink nodes can be computed efficiently and accurately. Our experimental results show that the proposed algorithm is two orders of magnitude faster than HSPICE without loss of accuracy and stability. The maximum error is within 0.4% of the exact delay time.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

Multiple supply voltage (MSV) is an effective scheme to achieve low power. Recent works in MSV are based on physical level and aim at reducing physical overheads, but all of them do not consider level converter, which is one of the most important issues in dual-vdd design. In this work, a logic and layout aware methodology and related algorithms combining voltage assignment and placement are proposed to minimize the number of level converters and to implement voltage islands with minimal physical overheads. Experimental results show that our approach uses much fewer level converters (reduced by 83.23% on average) and improves the power savings by 16% on average compared to the previous approach [1]. Furthermore, the methodology is able to produce feasible placement with a small impact to traditional placement goals.

By taking advantages of deep learning and reinforcement learning, ADNet (Action Decision Network) outperforms other approaches. However, its speed and performance are still limited by factors such as unreliable confidence score estimation and redundant historical actions. To address the above limitations, a faster and more accurate approach named Faster-ADNet is proposed in this paper. By optimizing the tracking process via a status re-identification network, the proposed approach is more efficient and 6 times faster than ADNet. At the same time, the accuracy and stability are enhanced by historical actions removal. Experiments demonstrate the advantages of Faster-ADNet.