Loop optimization plays an important role in compiler optimization and program transformation. Many sophisticated techniques such as loop-invariance code motion, loop restructuring and loop fusion have been developed. This paper introduces a novel technique called loop quasi-invariance code motion. It is a generalization of standard loop-invariance code motion, but based on loop quasi-invariance analysis. Loop quasi-invariance is similar to standard loop-invariance but allows for a finite number of iterations before computations in a loop become invariant. In this paper we define the notion of loop quasi-invariance, present an algorithm for statically computing the optimal unfolding length in While-programs and give a transformation method. Our method can increase the accuracy of program analyses and improve the efficiency of programs by making loops smaller and faster. Our technique is well-suited as supporting transformation in compilers, partial evaluators, and other program transformers.

Non-orthogonal multiple access (NOMA) is a promising multiple access scheme for further improving the spectrum efficiency compared to orthogonal multiple access (OMA) in the 5th Generation (5G) mobile communication systems. As inter-user interference cancellers for NOMA, two kinds of receiver structures are considered. One is the reduced complexity-maximum likelihood receiver (R-ML) and the other is the codeword level interference canceller (CWIC). In this paper, we show that the R-ML is superior to the CWIC in terms of scheduling flexibility. In addition, we propose a link to system (L2S) mapping scheme for the R-ML to conduct a system level evaluation, and show that the proposed scheme accurately predicts the block error rate (BLER) performance of the R-ML. The proposed L2S mapping scheme also demonstrates that the system level throughput performance of the R-ML is higher than that for the CWIC thanks to the scheduling flexibility.

With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.

We present a novel adversarial, end-to-end framework based on Creative-GAN to generate artistic music conditioned on dance videos. Our proposed framework takes the visual and motion posture data as input, and then adopts a quantized vector as the audio representation to generate complex music corresponding to input. However, the GAN algorithm just imitate and reproduce works what humans have created, instead of generating something new and creative. Therefore, we newly introduce Creative-GAN, which extends the original GAN framework to two discriminators, one is to determine whether it is real music, and the other is to classify music style. The paper shows that our proposed Creative-GAN can generate novel and interesting music which is not found in the training dataset. To evaluate our model, a comprehensive evaluation scheme is introduced to make subjective and objective evaluation. Compared with the advanced methods, our experimental results performs better in measureing the music rhythm, generation diversity, dance-music correlation and overall quality of generated music.

As power consumption of the clock tree dominates over 40% of the total power in modern high performance VLSI designs, measures must be taken to keep it under control. One of the most effective methods is based on clock gating to shut off the clock when the modules are idle. However, previous works on gated clock tree power minimization are mostly focused on clock routing and the improvements are often limited by the given registers placement. The purpose of this work is to navigate the registers during placement to further reduce the clock tree power based on clock gating. Our method performs activity-aware register clustering that reduces the clock tree power not only by clumping the registers into a smaller area, but also by pulling the registers with the similar activity patterns closely to shut off the clock more time for the resultant subtrees. In order to reduce the impact of signal nets wirelength and power due to register clustering, we apply the timing and activity based net weighting in [14], which reduces the nets switching power by assigning a combination of activity and timing weights to the nets with higher switching rates or more critical timing. To tradeoff the power dissipated by the clock tree and the control signal, we extend the idea of local ungating in [6] and propose an algorithm of gate control signal optimization, which still sets the gate enable signal high if a register is active for a number of consecutive clock cycles. Experimental results on a set of MCNC benchmarks show that our approach is able to reduce the power and total wirelength of clock tree greatly with minimal overheads.