The jaw movements can be measured by estimating the position and orientation of two small permanent magnets attached on the upper and lower jaws. It is a difficult problem to estimate the positions and orientations of the magnets from magnetic field because it is a typical inverse problem. The back propagation neural networks (BPNN) are applicable to solve this problem in short processing time. But its precision is not enough to apply to practical measurement. In the other hand, precise estimation is possible by using the nonlinear least-square (NLS) method. However, it takes long processing time for iterative calculation, and the solutions may be trapped in the local minima. In this paper, we propose a precise and fast measurement system which makes use of the estimation algorithm combining BPNN with NLS method. In this method, the BPNN performs an approximate estimation of magnet parameters in short processing time, and its result is used as the initial value of iterative calculation of NLS method. The cost function is solved by Gauss-Newton iteration algorithm. Precision, processing time and noise immunity were examined by computer simulations. These results shows the proposed system has satisfactory ability to be applied to practical measurement.

Three dimensional (3D) integrated circuits (ICs) have the potential to significantly enhance VLSI chip performance, functionality and device packing density. Interconnects delay and signal integrity issues are critical in chip design. In this paper, we extend the idea of redundant via insertion of conventional 2D ICs and propose an approach for vias insertion/placement in 3D ICs to minimize the propagation delay of interconnects with the consideration of signal integrity. The simulation results based on a 65 nm CMOS technology demonstrate that our approach in general can result in a 9% improvement in average delay and a 26% decrease in reflection coefficient. It is also shown that the proposed approach can be more effective for interconnects delay improvement when it is integrated with the buffer insertion in 3D ICs.

The evolution of VLSI chips towards larger die size, smaller feature size and faster clock speed makes the clock distribution an increasingly important issue. In this paper, we propose a new clock distribution network (CDN), namely Variant X-Tree, based on the idea of X-Architecture proposed recently for efficient wiring within VLSI chips. The Variant X-Tree CDN keeps the nice properties of equal-clock-path and symmetric structure of the typical H-Tree CDN, but results in both a lower maximal clock delay and a lower clock skew than its H-Tree counterpart, as verified by an extensive simulation study that incorporates simultaneously the effects of process variations and on-chip inductance. We also propose a closed-form statistical models for evaluating the skew and delay of the Variant X-Tree CDN. The comparison between the theoretical results and the simulation results indicates that the proposed statistical models can be used to efficiently and rapidly evaluate the performance of the variant X-Tree CDNs.

A current continuity equation is proposed as the additional equation for the GTD-MM hybrid technique formulation to acquire the uniqueness of the solution which were nonexistent in the conventional formulation with the matching-point equation. The current continuity equation, which ensures the current continuity and satisfies the boundary condition, can directly be written down through equating the MM-region current to the GTD-region current at the regions boundary. It is proved that the current continuity equation is equivalent to the matching-point equation of special case when the matching-point located very close to the boundary, which were able to give the best solution in the conventional formulation with the matching-point equation as explained by Burnside et al. The validity of the new equation is confirmed through the numerical results.

Non-orthogonal multiple access (NOMA) is a promising multiple access scheme for further improving the spectrum efficiency compared to orthogonal multiple access (OMA) in the 5th Generation (5G) mobile communication systems. As inter-user interference cancellers for NOMA, two kinds of receiver structures are considered. One is the reduced complexity-maximum likelihood receiver (R-ML) and the other is the codeword level interference canceller (CWIC). In this paper, we show that the R-ML is superior to the CWIC in terms of scheduling flexibility. In addition, we propose a link to system (L2S) mapping scheme for the R-ML to conduct a system level evaluation, and show that the proposed scheme accurately predicts the block error rate (BLER) performance of the R-ML. The proposed L2S mapping scheme also demonstrates that the system level throughput performance of the R-ML is higher than that for the CWIC thanks to the scheduling flexibility.

A new hybrid brain-computer interface (BCI), which is based on sequential controls by eye tracking and steady-state visual evoked potentials (SSVEPs), has been proposed for high-speed spelling in virtual reality (VR) with a 40-target virtual keyboard. During target selection, gaze point was first detected by an eye-tracking accessory. A 4-target block was then selected for further target selection by a 4-class SSVEP BCI. The system can type at a speed of 1.25 character/sec in a cue-guided target selection task. Online experiments on three subjects achieved an averaged information transfer rate (ITR) of 360.7 bits/min.

This paper provides a prototype neural prosthesis system dedicated to restoring continence and micturition function for patients with lower urinary tract diseases, such as detrusor hyperreflexia and detrusor-sphincter dyssynergia. This system consists of an ultra low-noise electroneurogram (ENG) signal recording module, a bi-phasic electrical stimulator module and a control unit for closed-loop bladder monitoring and controlling. In order to record extremely weak ENG signal from extradural sacral nerve roots, the system provides a programmable gain from 80 dB to 117 dB. By combining of advantages of commercial-off-the-shelf (COTS) electronics and custom designed IC, the recording front-end acquires a fairly low input-referred noise (IRN) of 0.69 μVrms under 300 Hz to 3 kHz and high area-efficiency. An on-chip multi-steps single slope analog-to-digital converter (ADC) is used to digitize the ENG signals at sampling rate of 10 kSPS and achieves an effective number of bits (ENOB) of 12.5. A bi-phasic current stimulus generator with wide voltage supply range (±0.9 V to ±12.5 V) and variable output current amplitude (0-500 μA) is introduced to overcome patient-depended impedance between electrode and tissue electrolyte. The total power consumption of the entire system is 5.61 mW. Recording and stimulation function of this system is switched by control unit with time division multiplexing strategy. The functionality of this proposed prototype system has been successfully verified through in-vivo experiments from dogs extradural sacral nerve roots.