Navigating Register Placement for Low Power Clock Network Design
Summary :
With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E88-A No.12 pp.3405-3411
- Publication Date
- 2005/12/01
- Publicized
- Online ISSN
- DOI
- 10.1093/ietfec/e88-a.12.3405
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Floorplan and Placement
Authors
Keyword
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Yongqiang LU, Chin-Ngai SZE, Xianlong HONG, Qiang ZHOU, Yici CAI, Liang HUANG, Jiang HU, "Navigating Register Placement for Low Power Clock Network Design" in IEICE TRANSACTIONS on Fundamentals,
vol. E88-A, no. 12, pp. 3405-3411, December 2005, doi: 10.1093/ietfec/e88-a.12.3405.
Abstract: With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1093/ietfec/e88-a.12.3405/_p
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@ARTICLE{e88-a_12_3405,
author={Yongqiang LU, Chin-Ngai SZE, Xianlong HONG, Qiang ZHOU, Yici CAI, Liang HUANG, Jiang HU, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Navigating Register Placement for Low Power Clock Network Design},
year={2005},
volume={E88-A},
number={12},
pages={3405-3411},
abstract={With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.},
keywords={},
doi={10.1093/ietfec/e88-a.12.3405},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Navigating Register Placement for Low Power Clock Network Design
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 3405
EP - 3411
AU - Yongqiang LU
AU - Chin-Ngai SZE
AU - Xianlong HONG
AU - Qiang ZHOU
AU - Yici CAI
AU - Liang HUANG
AU - Jiang HU
PY - 2005
DO - 10.1093/ietfec/e88-a.12.3405
JO - IEICE TRANSACTIONS on Fundamentals
SN -
VL - E88-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2005
AB - With VLSI design development, the increasingly severe power problem requests to minimize clock routing wirelength so that both power consumption and power supply noise can be alleviated. In contrast to most of traditional works that handle this problem only in clock routing, we propose to navigate standard cell register placement to locations that enable further less clock routing wirelength and power. To minimize adverse impacts to conventional cell placement goals such as signal net wirelength and critical path delay, the register placement is carried out in the context of a quadratic placement. The proposed technique is particularly effective for the recently popular prescribed skew clock routing. Experiments on benchmark circuits show encouraging results.
ER -
English
