IEICE TRANSACTIONS on Information
Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture
Summary :
An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.314-323
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.314
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Design Methodology
Authors
Keyword
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Ce LI, Yiping DONG, Takahiro WATANABE, "Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 2, pp. 314-323, February 2012, doi: 10.1587/transinf.E95.D.314.
Abstract: An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.314/_p
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@ARTICLE{e95-d_2_314,
author={Ce LI, Yiping DONG, Takahiro WATANABE, },
journal={IEICE TRANSACTIONS on Information},
title={Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture},
year={2012},
volume={E95-D},
number={2},
pages={314-323},
abstract={An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.},
keywords={},
doi={10.1587/transinf.E95.D.314},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Region-Oriented Placement Algorithm for Coarse-Grained Power-Gating FPGA Architecture
T2 - IEICE TRANSACTIONS on Information
SP - 314
EP - 323
AU - Ce LI
AU - Yiping DONG
AU - Takahiro WATANABE
PY - 2012
DO - 10.1587/transinf.E95.D.314
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - An FPGA plays an essential role in industrial products due to its fast, stable and flexible features. But the power consumption of FPGAs used in portable devices is one of critical issues. Top-down hierarchical design method is commonly used in both ASIC and FPGA design. But, in the case where plural modules are integrated in an FPGA and some of them might be in sleep-mode, current FPGA architecture cannot be fully effective. In this paper, coarse-grained power gating FPGA architecture is proposed where a whole area of an FPGA is partitioned into several regions and power supply is controlled for each region, so that modules in sleep mode can be effectively power-off. We also propose a region oriented FPGA placement algorithm fitted to this user's hierarchical design based on VPR [1]. Simulation results show that this proposed method could reduce power consumption of FPGA by 38% on average by setting unused modules or regions in sleep mode.
ER -
English
