IEICE TRANSACTIONS on Information
A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms
Summary :
In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.
- Publication
- IEICE TRANSACTIONS on Information Vol.E95-D No.2 pp.403-412
- Publication Date
- 2012/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E95.D.403
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Application
Authors
Keyword
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Shuangqu HUANG, Xiaoyang ZENG, Yun CHEN, "A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms" in IEICE TRANSACTIONS on Information,
vol. E95-D, no. 2, pp. 403-412, February 2012, doi: 10.1587/transinf.E95.D.403.
Abstract: In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E95.D.403/_p
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@ARTICLE{e95-d_2_403,
author={Shuangqu HUANG, Xiaoyang ZENG, Yun CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms},
year={2012},
volume={E95-D},
number={2},
pages={403-412},
abstract={In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.},
keywords={},
doi={10.1587/transinf.E95.D.403},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - A Flexible LDPC Decoder Architecture Supporting TPMP and TDMP Decoding Algorithms
T2 - IEICE TRANSACTIONS on Information
SP - 403
EP - 412
AU - Shuangqu HUANG
AU - Xiaoyang ZENG
AU - Yun CHEN
PY - 2012
DO - 10.1587/transinf.E95.D.403
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E95-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2012
AB - In this paper a programmable and area-efficient decoder architecture supporting two decoding algorithms for Block-LDPC codes is presented. The novel decoder can be configured to decode in either TPMP or TDMP decoding mode according to different Block-LDPC codes, essentially combining the advantages of two decoding algorithms. With a regular and scalable data-path, a Reconfigurable Serial Processing Engine (RSPE) is proposed to achieve area efficiency. To verify our proposed architecture, a flexible LDPC decoder fully compliant to IEEE 802.16e applications is implemented on a 130 nm 1P8M CMOS technology with a total area of 6.3 mm2 and maximum operating frequency of 250 MHz. The chip dissipates 592 mW when operates at 250 MHz frequency and 1.2 V supply.
ER -
English
