A System-Level Network Virtual Platform for IPsec Processor Development

Chen-Chieh WANG; Chung-Ho CHEN

doi:10.1587/transinf.E96.D.1095

A System-Level Network Virtual Platform for IPsec Processor Development

Chen-Chieh WANG, Chung-Ho CHEN

Full Text Views

0

Cite this

Summary :

Developing a complex network accelerator like an IPsec processor is a great challenge. To this end, we propose a Network Virtual Platform ( NetVP ) that consists of one or more virtual host (vHOST) modules and virtual local area network (vLAN) modules to support electronic system level (ESL) top-down design flow as well as provide the on-line verification throughout the entire development process. The on-line verification capability of NetVP enables the designed target to communicate with a real network for system validation. For ESL top-down design flow, we also propose untimed and timed interfaces to support hardware/software co-simulation. In addition, the NetVP can be used in conjunction with any ESL development platform through the untimed/timed interface. System development that uses this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily. The NetVP can also be applied to the development of other kinds of network accelerators.

Publication: IEICE TRANSACTIONS on Information Vol.E96-D No.5 pp.1095-1104

Publication Date: 2013/05/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E96.D.1095

Type of Manuscript: PAPER

Category: Software Engineering

Cite this

Copy

Chen-Chieh WANG, Chung-Ho CHEN, "A System-Level Network Virtual Platform for IPsec Processor Development" in IEICE TRANSACTIONS on Information, vol. E96-D, no. 5, pp. 1095-1104, May 2013, doi: 10.1587/transinf.E96.D.1095.
Abstract: Developing a complex network accelerator like an IPsec processor is a great challenge. To this end, we propose a Network Virtual Platform ( NetVP ) that consists of one or more virtual host (vHOST) modules and virtual local area network (vLAN) modules to support electronic system level (ESL) top-down design flow as well as provide the on-line verification throughout the entire development process. The on-line verification capability of NetVP enables the designed target to communicate with a real network for system validation. For ESL top-down design flow, we also propose untimed and timed interfaces to support hardware/software co-simulation. In addition, the NetVP can be used in conjunction with any ESL development platform through the untimed/timed interface. System development that uses this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily. The NetVP can also be applied to the development of other kinds of network accelerators.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1095/_p

Copy

@ARTICLE{e96-d_5_1095,
author={Chen-Chieh WANG, Chung-Ho CHEN, },
journal={IEICE TRANSACTIONS on Information},
title={A System-Level Network Virtual Platform for IPsec Processor Development},
year={2013},
volume={E96-D},
number={5},
pages={1095-1104},
abstract={Developing a complex network accelerator like an IPsec processor is a great challenge. To this end, we propose a Network Virtual Platform ( NetVP ) that consists of one or more virtual host (vHOST) modules and virtual local area network (vLAN) modules to support electronic system level (ESL) top-down design flow as well as provide the on-line verification throughout the entire development process. The on-line verification capability of NetVP enables the designed target to communicate with a real network for system validation. For ESL top-down design flow, we also propose untimed and timed interfaces to support hardware/software co-simulation. In addition, the NetVP can be used in conjunction with any ESL development platform through the untimed/timed interface. System development that uses this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily. The NetVP can also be applied to the development of other kinds of network accelerators.},
keywords={},
doi={10.1587/transinf.E96.D.1095},
ISSN={1745-1361},
month={May},}

Copy

TY - JOUR
TI - A System-Level Network Virtual Platform for IPsec Processor Development
T2 - IEICE TRANSACTIONS on Information
SP - 1095
EP - 1104
AU - Chen-Chieh WANG
AU - Chung-Ho CHEN
PY - 2013
DO - 10.1587/transinf.E96.D.1095
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 5
JA - IEICE TRANSACTIONS on Information
Y1 - May 2013
AB - Developing a complex network accelerator like an IPsec processor is a great challenge. To this end, we propose a Network Virtual Platform ( NetVP ) that consists of one or more virtual host (vHOST) modules and virtual local area network (vLAN) modules to support electronic system level (ESL) top-down design flow as well as provide the on-line verification throughout the entire development process. The on-line verification capability of NetVP enables the designed target to communicate with a real network for system validation. For ESL top-down design flow, we also propose untimed and timed interfaces to support hardware/software co-simulation. In addition, the NetVP can be used in conjunction with any ESL development platform through the untimed/timed interface. System development that uses this NetVP is efficient and flexible since it allows the designer to explore design spaces such as the network bandwidth and system architecture easily. The NetVP can also be applied to the development of other kinds of network accelerators.
ER -