IEICE TRANSACTIONS on Information
A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards
Summary :
Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.8 pp.1645-1653
- Publication Date
- 2013/08/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.1645
- Type of Manuscript
- Special Section PAPER (Special Section on Reconfigurable Systems)
- Category
- Architecture
Authors
Son-Truong NGUYEN
The University of Electro-Communications
Masaaki KONDO
The University of Electro-Communications
Tomoya HIRAO
Kyushu University
Koji INOUE
Kyushu University
Keyword
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Son-Truong NGUYEN, Masaaki KONDO, Tomoya HIRAO, Koji INOUE, "A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 8, pp. 1645-1653, August 2013, doi: 10.1587/transinf.E96.D.1645.
Abstract: Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1645/_p
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@ARTICLE{e96-d_8_1645,
author={Son-Truong NGUYEN, Masaaki KONDO, Tomoya HIRAO, Koji INOUE, },
journal={IEICE TRANSACTIONS on Information},
title={A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards},
year={2013},
volume={E96-D},
number={8},
pages={1645-1653},
abstract={Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.},
keywords={},
doi={10.1587/transinf.E96.D.1645},
ISSN={1745-1361},
month={August},}
Copy
TY - JOUR
TI - A Prototype System for Many-Core Architecture SMYLEref with FPGA Evaluation Boards
T2 - IEICE TRANSACTIONS on Information
SP - 1645
EP - 1653
AU - Son-Truong NGUYEN
AU - Masaaki KONDO
AU - Tomoya HIRAO
AU - Koji INOUE
PY - 2013
DO - 10.1587/transinf.E96.D.1645
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2013
AB - Nowadays, the trend of developing micro-processor with hundreds of cores brings a promising prospect for embedded systems. Realizing a high performance and low power many-core processor is becoming a primary technical challenge. Generally, three major issues required to be resolved includes: 1) realizing efficient massively parallel processing, 2) reducing dynamic power consumption, and 3) improving software productivity. To deal with these issues, we propose a solution to use many low-performance but small and very low-power cores to obtain very high performance, and develop a referential many-core architecture and a program development environment. This paper introduces a many-core architecture named SMYLEref and its prototype system with off-the-shelf FPGA evaluation boards. The initial evaluation results of several SPLASH2 benchmark programs conducted on our developed 128-core platform are also presented and discussed in this paper.
ER -
English
