FPGA Implementation of Human Detection by HOG Features with AdaBoost

Keisuke DOHI; Kazuhiro NEGI; Yuichiro SHIBATA; Kiyoshi OGURI

doi:10.1587/transinf.E96.D.1676

IEICE TRANSACTIONS on Information

FPGA Implementation of Human Detection by HOG Features with AdaBoost

Keisuke DOHI, Kazuhiro NEGI, Yuichiro SHIBATA, Kiyoshi OGURI

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Summary :

We implement external memory-free deep pipelined FPGA implementation including HOG feature extraction and AdaBoost classification. To construct our design by compact FPGA, we introduce some simplifications of the algorithm and aggressive use of stream oriented architectures. We present comparison results between our simplified fixed-point scheme and an original floating-point scheme in terms of quality of results, and the results suggest the negative impact of the simplified scheme for hardware implementation is limited. We empirically show that, our system is able to detect human from 640480 VGA images at up to 112 FPS on a Xilinx Virtex-5 XC5VLX50 FPGA.

Publication: IEICE TRANSACTIONS on Information Vol.E96-D No.8 pp.1676-1684

Publication Date: 2013/08/01

Publicized

Online ISSN: 1745-1361

DOI: 10.1587/transinf.E96.D.1676

Type of Manuscript: Special Section PAPER (Special Section on Reconfigurable Systems)

Category: Application

Authors

Keisuke DOHI
  Nagasaki University
Kazuhiro NEGI
  Nagasaki University
Yuichiro SHIBATA
  Nagasaki University
Kiyoshi OGURI
  Nagasaki University

Keyword

histogram of oriented gradients, AdaBoost, human detection, FPGA

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Keisuke DOHI, Kazuhiro NEGI, Yuichiro SHIBATA, Kiyoshi OGURI, "FPGA Implementation of Human Detection by HOG Features with AdaBoost" in IEICE TRANSACTIONS on Information, vol. E96-D, no. 8, pp. 1676-1684, August 2013, doi: 10.1587/transinf.E96.D.1676.
Abstract: We implement external memory-free deep pipelined FPGA implementation including HOG feature extraction and AdaBoost classification. To construct our design by compact FPGA, we introduce some simplifications of the algorithm and aggressive use of stream oriented architectures. We present comparison results between our simplified fixed-point scheme and an original floating-point scheme in terms of quality of results, and the results suggest the negative impact of the simplified scheme for hardware implementation is limited. We empirically show that, our system is able to detect human from 640480 VGA images at up to 112 FPS on a Xilinx Virtex-5 XC5VLX50 FPGA.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.1676/_p

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@ARTICLE{e96-d_8_1676,
author={Keisuke DOHI, Kazuhiro NEGI, Yuichiro SHIBATA, Kiyoshi OGURI, },
journal={IEICE TRANSACTIONS on Information},
title={FPGA Implementation of Human Detection by HOG Features with AdaBoost},
year={2013},
volume={E96-D},
number={8},
pages={1676-1684},
abstract={We implement external memory-free deep pipelined FPGA implementation including HOG feature extraction and AdaBoost classification. To construct our design by compact FPGA, we introduce some simplifications of the algorithm and aggressive use of stream oriented architectures. We present comparison results between our simplified fixed-point scheme and an original floating-point scheme in terms of quality of results, and the results suggest the negative impact of the simplified scheme for hardware implementation is limited. We empirically show that, our system is able to detect human from 640480 VGA images at up to 112 FPS on a Xilinx Virtex-5 XC5VLX50 FPGA.},
keywords={},
doi={10.1587/transinf.E96.D.1676},
ISSN={1745-1361},
month={August},}

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TY - JOUR
TI - FPGA Implementation of Human Detection by HOG Features with AdaBoost
T2 - IEICE TRANSACTIONS on Information
SP - 1676
EP - 1684
AU - Keisuke DOHI
AU - Kazuhiro NEGI
AU - Yuichiro SHIBATA
AU - Kiyoshi OGURI
PY - 2013
DO - 10.1587/transinf.E96.D.1676
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 8
JA - IEICE TRANSACTIONS on Information
Y1 - August 2013
AB - We implement external memory-free deep pipelined FPGA implementation including HOG feature extraction and AdaBoost classification. To construct our design by compact FPGA, we introduce some simplifications of the algorithm and aggressive use of stream oriented architectures. We present comparison results between our simplified fixed-point scheme and an original floating-point scheme in terms of quality of results, and the results suggest the negative impact of the simplified scheme for hardware implementation is limited. We empirically show that, our system is able to detect human from 640480 VGA images at up to 112 FPS on a Xilinx Virtex-5 XC5VLX50 FPGA.
ER -

IEICE TRANSACTIONS on Information