NROM is one of the emerging non-volatile-memory technologies, which is promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the conventional fault replacement techniques, a novel fault masking technique is also exploited by considering the logical effects of physical defects when the customer's code is to be programmed. In order to maximize the possibilities of fault masking, a novel data inversion technique is proposed. The corresponding BIST architectures are also presented. According to experimental results, the repair rate and fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
Tsu-Lin LI
National Taiwan University of Science and Technology
Masaki HASHIZUME
The Univ. of Tokushima
Shyue-Kung LU
National Taiwan University of Science and Technology
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Tsu-Lin LI, Masaki HASHIZUME, Shyue-Kung LU, "An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 9, pp. 2026-2030, September 2013, doi: 10.1587/transinf.E96.D.2026.
Abstract: NROM is one of the emerging non-volatile-memory technologies, which is promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the conventional fault replacement techniques, a novel fault masking technique is also exploited by considering the logical effects of physical defects when the customer's code is to be programmed. In order to maximize the possibilities of fault masking, a novel data inversion technique is proposed. The corresponding BIST architectures are also presented. According to experimental results, the repair rate and fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.2026/_p
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@ARTICLE{e96-d_9_2026,
author={Tsu-Lin LI, Masaki HASHIZUME, Shyue-Kung LU, },
journal={IEICE TRANSACTIONS on Information},
title={An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs},
year={2013},
volume={E96-D},
number={9},
pages={2026-2030},
abstract={NROM is one of the emerging non-volatile-memory technologies, which is promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the conventional fault replacement techniques, a novel fault masking technique is also exploited by considering the logical effects of physical defects when the customer's code is to be programmed. In order to maximize the possibilities of fault masking, a novel data inversion technique is proposed. The corresponding BIST architectures are also presented. According to experimental results, the repair rate and fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.},
keywords={},
doi={10.1587/transinf.E96.D.2026},
ISSN={1745-1361},
month={September},}
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TY - JOUR
TI - An Efficient Test and Repair Flow for Yield Enhancement of One-Time-Programming NROM-Based ROMs
T2 - IEICE TRANSACTIONS on Information
SP - 2026
EP - 2030
AU - Tsu-Lin LI
AU - Masaki HASHIZUME
AU - Shyue-Kung LU
PY - 2013
DO - 10.1587/transinf.E96.D.2026
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 9
JA - IEICE TRANSACTIONS on Information
Y1 - September 2013
AB - NROM is one of the emerging non-volatile-memory technologies, which is promising for replacing current floating-gate-based non-volatile memory such as flash memory. In order to raise the fabrication yield and enhance its reliability, a novel test and repair flow is proposed in this paper. Instead of the conventional fault replacement techniques, a novel fault masking technique is also exploited by considering the logical effects of physical defects when the customer's code is to be programmed. In order to maximize the possibilities of fault masking, a novel data inversion technique is proposed. The corresponding BIST architectures are also presented. According to experimental results, the repair rate and fabrication yield can be improved significantly. Moreover, the incurred hardware overhead is almost negligible.
ER -