IEICE TRANSACTIONS on Information
Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures
Summary :
The efficiency of ubiquitous SIMD (Single Instruction Multiple Data) media processors is seriously limited by the bottleneck effect of the scalar kernels in media applications. To solve this problem, a dual-core framework, composed of a micro control unit and an instruction buffer, is proposed. This framework can dynamically decouple the scalar and vector pipelines of the original single-core SIMD architecture into two free-running cores. Thus, the bottleneck effect can be eliminated by effectively exploiting the parallelism between scalar and vector kernels. The dual-core framework achieves the best attributes of both single-core and dual-core SIMD architectures. Experimental results exhibit an average performance improvement of 33%, at an area overhead of 4.26%. What's more, with the increase of the SIMD width, higher performance gain and lower cost can be expected.
- Publication
- IEICE TRANSACTIONS on Information Vol.E96-D No.2 pp.365-369
- Publication Date
- 2013/02/01
- Publicized
- Online ISSN
- 1745-1361
- DOI
- 10.1587/transinf.E96.D.365
- Type of Manuscript
- LETTER
- Category
- Computer System
Authors
Keyword
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Yaohua WANG, Shuming CHEN, Hu CHEN, Jianghua WAN, Kai ZHANG, Sheng LIU, "Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures" in IEICE TRANSACTIONS on Information,
vol. E96-D, no. 2, pp. 365-369, February 2013, doi: 10.1587/transinf.E96.D.365.
Abstract: The efficiency of ubiquitous SIMD (Single Instruction Multiple Data) media processors is seriously limited by the bottleneck effect of the scalar kernels in media applications. To solve this problem, a dual-core framework, composed of a micro control unit and an instruction buffer, is proposed. This framework can dynamically decouple the scalar and vector pipelines of the original single-core SIMD architecture into two free-running cores. Thus, the bottleneck effect can be eliminated by effectively exploiting the parallelism between scalar and vector kernels. The dual-core framework achieves the best attributes of both single-core and dual-core SIMD architectures. Experimental results exhibit an average performance improvement of 33%, at an area overhead of 4.26%. What's more, with the increase of the SIMD width, higher performance gain and lower cost can be expected.
URL: https://global.ieice.org/en_transactions/information/10.1587/transinf.E96.D.365/_p
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@ARTICLE{e96-d_2_365,
author={Yaohua WANG, Shuming CHEN, Hu CHEN, Jianghua WAN, Kai ZHANG, Sheng LIU, },
journal={IEICE TRANSACTIONS on Information},
title={Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures},
year={2013},
volume={E96-D},
number={2},
pages={365-369},
abstract={The efficiency of ubiquitous SIMD (Single Instruction Multiple Data) media processors is seriously limited by the bottleneck effect of the scalar kernels in media applications. To solve this problem, a dual-core framework, composed of a micro control unit and an instruction buffer, is proposed. This framework can dynamically decouple the scalar and vector pipelines of the original single-core SIMD architecture into two free-running cores. Thus, the bottleneck effect can be eliminated by effectively exploiting the parallelism between scalar and vector kernels. The dual-core framework achieves the best attributes of both single-core and dual-core SIMD architectures. Experimental results exhibit an average performance improvement of 33%, at an area overhead of 4.26%. What's more, with the increase of the SIMD width, higher performance gain and lower cost can be expected.},
keywords={},
doi={10.1587/transinf.E96.D.365},
ISSN={1745-1361},
month={February},}
Copy
TY - JOUR
TI - Dual-Core Framework: Eliminating the Bottleneck Effect of Scalar Kernels on SIMD Architectures
T2 - IEICE TRANSACTIONS on Information
SP - 365
EP - 369
AU - Yaohua WANG
AU - Shuming CHEN
AU - Hu CHEN
AU - Jianghua WAN
AU - Kai ZHANG
AU - Sheng LIU
PY - 2013
DO - 10.1587/transinf.E96.D.365
JO - IEICE TRANSACTIONS on Information
SN - 1745-1361
VL - E96-D
IS - 2
JA - IEICE TRANSACTIONS on Information
Y1 - February 2013
AB - The efficiency of ubiquitous SIMD (Single Instruction Multiple Data) media processors is seriously limited by the bottleneck effect of the scalar kernels in media applications. To solve this problem, a dual-core framework, composed of a micro control unit and an instruction buffer, is proposed. This framework can dynamically decouple the scalar and vector pipelines of the original single-core SIMD architecture into two free-running cores. Thus, the bottleneck effect can be eliminated by effectively exploiting the parallelism between scalar and vector kernels. The dual-core framework achieves the best attributes of both single-core and dual-core SIMD architectures. Experimental results exhibit an average performance improvement of 33%, at an area overhead of 4.26%. What's more, with the increase of the SIMD width, higher performance gain and lower cost can be expected.
ER -
English
