Design Curves for Linear Phase, Low-Pass Impedance Matching Networks

Isao ENDO; Suketoshi SUZUKI; Michio AKIYAMA

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Isao ENDO, Suketoshi SUZUKI, Michio AKIYAMA, "Design Curves for Linear Phase, Low-Pass Impedance Matching Networks" in IEICE TRANSACTIONS on transactions, vol. E63-E, no. 10, pp. 772-773, October 1980, doi: .
Abstract: Simple design curves are presented for linear phase, low-pass impedance matching networks. A parallel RC and an RLC load are considered. Using the design curves, we can easily determine the maximum DC gain K for a given load.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e63-e_10_772/_p

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@ARTICLE{e63-e_10_772,
author={Isao ENDO, Suketoshi SUZUKI, Michio AKIYAMA, },
journal={IEICE TRANSACTIONS on transactions},
title={Design Curves for Linear Phase, Low-Pass Impedance Matching Networks},
year={1980},
volume={E63-E},
number={10},
pages={772-773},
abstract={Simple design curves are presented for linear phase, low-pass impedance matching networks. A parallel RC and an RLC load are considered. Using the design curves, we can easily determine the maximum DC gain K for a given load.},
keywords={},
doi={},
ISSN={},
month={October},}

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TY - JOUR
TI - Design Curves for Linear Phase, Low-Pass Impedance Matching Networks
T2 - IEICE TRANSACTIONS on transactions
SP - 772
EP - 773
AU - Isao ENDO
AU - Suketoshi SUZUKI
AU - Michio AKIYAMA
PY - 1980
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E63-E
IS - 10
JA - IEICE TRANSACTIONS on transactions
Y1 - October 1980
AB - Simple design curves are presented for linear phase, low-pass impedance matching networks. A parallel RC and an RLC load are considered. Using the design curves, we can easily determine the maximum DC gain K for a given load.
ER -