A Study of High-Speed FFT Using Highly Multi-Dimensional Memory Structure

Shigenori SHIMIZU; Misao KITAGAWA

A Study of High-Speed FFT Using Highly Multi-Dimensional Memory Structure

Shigenori SHIMIZU, Misao KITAGAWA

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In this paper, an algorithm for implementing a high-speed FFT processor and the memory structure relating with it are mainly discussed. The problem to be considered when implementing a hard-wired high-speed FFT processor will be as follows: (1) How to simplify the decision of data addresses to be accessed. (2) How to avoid the memory access conflict when introducing the parallelization of memory. New method presented in this paper gives a drastic solution to them. Namely, utilizing the proposed memory structure allows any number of butterfly computations as well as single one to be carried out substantially in only one memory cycle. Furthermore, there is no theoretical restriction in any level of parallelization. Therefore, it is easy to implement the FFT processor having a reasonable throughput for particular application. The discussion in this paper is primarily proceeded from the hardware standpoint of implementation. However, there is no essential disparity between the proposed organization and that of conventional computers. The only difference between them is a conceptual one with respect to memory structure. Thus the presented method is useful enough for implementation of the algorithm on a conventional computer system such as multi-processors, and for its implementation by hardware as well.

Publication: IEICE TRANSACTIONS on transactions Vol.E64-E No.3 pp.160-167

Publication Date: 1981/03/25

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Type of Manuscript: PAPER

Category: Data Processing

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Shigenori SHIMIZU
Misao KITAGAWA

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Shigenori SHIMIZU, Misao KITAGAWA, "A Study of High-Speed FFT Using Highly Multi-Dimensional Memory Structure" in IEICE TRANSACTIONS on transactions, vol. E64-E, no. 3, pp. 160-167, March 1981, doi: .
Abstract: In this paper, an algorithm for implementing a high-speed FFT processor and the memory structure relating with it are mainly discussed. The problem to be considered when implementing a hard-wired high-speed FFT processor will be as follows: (1) How to simplify the decision of data addresses to be accessed. (2) How to avoid the memory access conflict when introducing the parallelization of memory. New method presented in this paper gives a drastic solution to them. Namely, utilizing the proposed memory structure allows any number of butterfly computations as well as single one to be carried out substantially in only one memory cycle. Furthermore, there is no theoretical restriction in any level of parallelization. Therefore, it is easy to implement the FFT processor having a reasonable throughput for particular application. The discussion in this paper is primarily proceeded from the hardware standpoint of implementation. However, there is no essential disparity between the proposed organization and that of conventional computers. The only difference between them is a conceptual one with respect to memory structure. Thus the presented method is useful enough for implementation of the algorithm on a conventional computer system such as multi-processors, and for its implementation by hardware as well.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e64-e_3_160/_p

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@ARTICLE{e64-e_3_160,
author={Shigenori SHIMIZU, Misao KITAGAWA, },
journal={IEICE TRANSACTIONS on transactions},
title={A Study of High-Speed FFT Using Highly Multi-Dimensional Memory Structure},
year={1981},
volume={E64-E},
number={3},
pages={160-167},
abstract={In this paper, an algorithm for implementing a high-speed FFT processor and the memory structure relating with it are mainly discussed. The problem to be considered when implementing a hard-wired high-speed FFT processor will be as follows: (1) How to simplify the decision of data addresses to be accessed. (2) How to avoid the memory access conflict when introducing the parallelization of memory. New method presented in this paper gives a drastic solution to them. Namely, utilizing the proposed memory structure allows any number of butterfly computations as well as single one to be carried out substantially in only one memory cycle. Furthermore, there is no theoretical restriction in any level of parallelization. Therefore, it is easy to implement the FFT processor having a reasonable throughput for particular application. The discussion in this paper is primarily proceeded from the hardware standpoint of implementation. However, there is no essential disparity between the proposed organization and that of conventional computers. The only difference between them is a conceptual one with respect to memory structure. Thus the presented method is useful enough for implementation of the algorithm on a conventional computer system such as multi-processors, and for its implementation by hardware as well.},
keywords={},
doi={},
ISSN={},
month={March},}

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TY - JOUR
TI - A Study of High-Speed FFT Using Highly Multi-Dimensional Memory Structure
T2 - IEICE TRANSACTIONS on transactions
SP - 160
EP - 167
AU - Shigenori SHIMIZU
AU - Misao KITAGAWA
PY - 1981
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E64-E
IS - 3
JA - IEICE TRANSACTIONS on transactions
Y1 - March 1981
AB - In this paper, an algorithm for implementing a high-speed FFT processor and the memory structure relating with it are mainly discussed. The problem to be considered when implementing a hard-wired high-speed FFT processor will be as follows: (1) How to simplify the decision of data addresses to be accessed. (2) How to avoid the memory access conflict when introducing the parallelization of memory. New method presented in this paper gives a drastic solution to them. Namely, utilizing the proposed memory structure allows any number of butterfly computations as well as single one to be carried out substantially in only one memory cycle. Furthermore, there is no theoretical restriction in any level of parallelization. Therefore, it is easy to implement the FFT processor having a reasonable throughput for particular application. The discussion in this paper is primarily proceeded from the hardware standpoint of implementation. However, there is no essential disparity between the proposed organization and that of conventional computers. The only difference between them is a conceptual one with respect to memory structure. Thus the presented method is useful enough for implementation of the algorithm on a conventional computer system such as multi-processors, and for its implementation by hardware as well.
ER -