A Digital CCD Field Memory for Video Signal Processing

Tadakuni NARABU; Hideo KANBE; Miaki NAKASHIO; Maki SATO; Takeo HASHIMOTO

A Digital CCD Field Memory for Video Signal Processing

Tadakuni NARABU, Hideo KANBE, Miaki NAKASHIO, Maki SATO, Takeo HASHIMOTO

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A CCD memory was implemented and its fundamental operation was confirmed. This memory is the first digital CCD field memory for video signal processing. It can read and write simultaneously at unusually high frequency such as 14.3 MHz in spite of having large capacity such as 195 k bits. This memory is made of one block of serial-parallel-serial structure. The ship size is 9.00 mm (H)5.5 mm (V). It was fabricated by n-channel CCD process using the three-level polysilicon technology. The thickness of gate oxide is 1000 . We developed CCD's of new structure for serial registers to obtain high horizontal bit density keeping high charge transfer efficiency. The serial registers have 768 effective bits and the length per bit is 10 µm/bit. The transfer efficiency was found to be more than 0.99997. Input clock pulses of the serial registers are 2-phase, 9 Vp-p. Parallel registers employ an operation of 6-phase electrode-per-bit, which contributes high vertical bit density. The clock generator and clock drivers for parallel registers are on-chip, and the levels of input clock pulses for them are TTL compatible. This memory generates reference signals, which identify digital signals of 1 or 0 at an external sense amplifier. The amplitude of the output signal is 200 m Vp-p.

Publication: IEICE TRANSACTIONS on transactions Vol.E66-E No.9 pp.543-549

Publication Date: 1983/09/25

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Type of Manuscript: PAPER

Category: Integrated Circuits

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Tadakuni NARABU
Hideo KANBE
Miaki NAKASHIO
Maki SATO
Takeo HASHIMOTO

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Tadakuni NARABU, Hideo KANBE, Miaki NAKASHIO, Maki SATO, Takeo HASHIMOTO, "A Digital CCD Field Memory for Video Signal Processing" in IEICE TRANSACTIONS on transactions, vol. E66-E, no. 9, pp. 543-549, September 1983, doi: .
Abstract: A CCD memory was implemented and its fundamental operation was confirmed. This memory is the first digital CCD field memory for video signal processing. It can read and write simultaneously at unusually high frequency such as 14.3 MHz in spite of having large capacity such as 195 k bits. This memory is made of one block of serial-parallel-serial structure. The ship size is 9.00 mm (H)5.5 mm (V). It was fabricated by n-channel CCD process using the three-level polysilicon technology. The thickness of gate oxide is 1000 . We developed CCD's of new structure for serial registers to obtain high horizontal bit density keeping high charge transfer efficiency. The serial registers have 768 effective bits and the length per bit is 10 µm/bit. The transfer efficiency was found to be more than 0.99997. Input clock pulses of the serial registers are 2-phase, 9 Vp-p. Parallel registers employ an operation of 6-phase electrode-per-bit, which contributes high vertical bit density. The clock generator and clock drivers for parallel registers are on-chip, and the levels of input clock pulses for them are TTL compatible. This memory generates reference signals, which identify digital signals of 1 or 0 at an external sense amplifier. The amplitude of the output signal is 200 m Vp-p.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e66-e_9_543/_p

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@ARTICLE{e66-e_9_543,
author={Tadakuni NARABU, Hideo KANBE, Miaki NAKASHIO, Maki SATO, Takeo HASHIMOTO, },
journal={IEICE TRANSACTIONS on transactions},
title={A Digital CCD Field Memory for Video Signal Processing},
year={1983},
volume={E66-E},
number={9},
pages={543-549},
abstract={A CCD memory was implemented and its fundamental operation was confirmed. This memory is the first digital CCD field memory for video signal processing. It can read and write simultaneously at unusually high frequency such as 14.3 MHz in spite of having large capacity such as 195 k bits. This memory is made of one block of serial-parallel-serial structure. The ship size is 9.00 mm (H)5.5 mm (V). It was fabricated by n-channel CCD process using the three-level polysilicon technology. The thickness of gate oxide is 1000 . We developed CCD's of new structure for serial registers to obtain high horizontal bit density keeping high charge transfer efficiency. The serial registers have 768 effective bits and the length per bit is 10 µm/bit. The transfer efficiency was found to be more than 0.99997. Input clock pulses of the serial registers are 2-phase, 9 Vp-p. Parallel registers employ an operation of 6-phase electrode-per-bit, which contributes high vertical bit density. The clock generator and clock drivers for parallel registers are on-chip, and the levels of input clock pulses for them are TTL compatible. This memory generates reference signals, which identify digital signals of 1 or 0 at an external sense amplifier. The amplitude of the output signal is 200 m Vp-p.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - A Digital CCD Field Memory for Video Signal Processing
T2 - IEICE TRANSACTIONS on transactions
SP - 543
EP - 549
AU - Tadakuni NARABU
AU - Hideo KANBE
AU - Miaki NAKASHIO
AU - Maki SATO
AU - Takeo HASHIMOTO
PY - 1983
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E66-E
IS - 9
JA - IEICE TRANSACTIONS on transactions
Y1 - September 1983
AB - A CCD memory was implemented and its fundamental operation was confirmed. This memory is the first digital CCD field memory for video signal processing. It can read and write simultaneously at unusually high frequency such as 14.3 MHz in spite of having large capacity such as 195 k bits. This memory is made of one block of serial-parallel-serial structure. The ship size is 9.00 mm (H)5.5 mm (V). It was fabricated by n-channel CCD process using the three-level polysilicon technology. The thickness of gate oxide is 1000 . We developed CCD's of new structure for serial registers to obtain high horizontal bit density keeping high charge transfer efficiency. The serial registers have 768 effective bits and the length per bit is 10 µm/bit. The transfer efficiency was found to be more than 0.99997. Input clock pulses of the serial registers are 2-phase, 9 Vp-p. Parallel registers employ an operation of 6-phase electrode-per-bit, which contributes high vertical bit density. The clock generator and clock drivers for parallel registers are on-chip, and the levels of input clock pulses for them are TTL compatible. This memory generates reference signals, which identify digital signals of 1 or 0 at an external sense amplifier. The amplitude of the output signal is 200 m Vp-p.
ER -