Failure Rate Prediction Method for LSIs

Kiyoshi OGAWA; Yoshimitsu SAKAGAWA; Yoshio SUNOHARA

Failure Rate Prediction Method for LSIs

Kiyoshi OGAWA, Yoshimitsu SAKAGAWA, Yoshio SUNOHARA

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This paper proposes, as a new LSI reliability estimation method, a procedure for estimating the failure rate of LSI by classifying failures according to failure modes and by expressing the failure rates as functions of the LSI design parameters. As a concrete example, bipolar logic LSIs and MOSRAMs were taken up. Their respective failure modes and the design parameter dependences for the failure rates were considered, in order to obtain the relations between the integration density and the failures. As a result, it was clarified that the failure rate per gate for bipolar logic LSI was inversely proportional to (the number of gates)^0.4 and that the failure rate per bit for MOSRAM was inversely proportional to (the number of bits)^0.7. And it was concluded that the dominant failure modes will be in the metallization for the bipolar logic LSI and in surface degradation for the MOSRAM. Thus, new LSI reliability estimation was carried out. And the technical problems to solve or new technical targets to study in order to improve the reliability of high density LSIs were clarified.

Publication: IEICE TRANSACTIONS on transactions Vol.E66-E No.9 pp.550-556

Publication Date: 1983/09/25

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Type of Manuscript: PAPER

Category: Integrated Circuits

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Kiyoshi OGAWA
Yoshimitsu SAKAGAWA
Yoshio SUNOHARA

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Kiyoshi OGAWA, Yoshimitsu SAKAGAWA, Yoshio SUNOHARA, "Failure Rate Prediction Method for LSIs" in IEICE TRANSACTIONS on transactions, vol. E66-E, no. 9, pp. 550-556, September 1983, doi: .
Abstract: This paper proposes, as a new LSI reliability estimation method, a procedure for estimating the failure rate of LSI by classifying failures according to failure modes and by expressing the failure rates as functions of the LSI design parameters. As a concrete example, bipolar logic LSIs and MOSRAMs were taken up. Their respective failure modes and the design parameter dependences for the failure rates were considered, in order to obtain the relations between the integration density and the failures. As a result, it was clarified that the failure rate per gate for bipolar logic LSI was inversely proportional to (the number of gates)^0.4 and that the failure rate per bit for MOSRAM was inversely proportional to (the number of bits)^0.7. And it was concluded that the dominant failure modes will be in the metallization for the bipolar logic LSI and in surface degradation for the MOSRAM. Thus, new LSI reliability estimation was carried out. And the technical problems to solve or new technical targets to study in order to improve the reliability of high density LSIs were clarified.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e66-e_9_550/_p

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@ARTICLE{e66-e_9_550,
author={Kiyoshi OGAWA, Yoshimitsu SAKAGAWA, Yoshio SUNOHARA, },
journal={IEICE TRANSACTIONS on transactions},
title={Failure Rate Prediction Method for LSIs},
year={1983},
volume={E66-E},
number={9},
pages={550-556},
abstract={This paper proposes, as a new LSI reliability estimation method, a procedure for estimating the failure rate of LSI by classifying failures according to failure modes and by expressing the failure rates as functions of the LSI design parameters. As a concrete example, bipolar logic LSIs and MOSRAMs were taken up. Their respective failure modes and the design parameter dependences for the failure rates were considered, in order to obtain the relations between the integration density and the failures. As a result, it was clarified that the failure rate per gate for bipolar logic LSI was inversely proportional to (the number of gates)^0.4 and that the failure rate per bit for MOSRAM was inversely proportional to (the number of bits)^0.7. And it was concluded that the dominant failure modes will be in the metallization for the bipolar logic LSI and in surface degradation for the MOSRAM. Thus, new LSI reliability estimation was carried out. And the technical problems to solve or new technical targets to study in order to improve the reliability of high density LSIs were clarified.},
keywords={},
doi={},
ISSN={},
month={September},}

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TY - JOUR
TI - Failure Rate Prediction Method for LSIs
T2 - IEICE TRANSACTIONS on transactions
SP - 550
EP - 556
AU - Kiyoshi OGAWA
AU - Yoshimitsu SAKAGAWA
AU - Yoshio SUNOHARA
PY - 1983
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E66-E
IS - 9
JA - IEICE TRANSACTIONS on transactions
Y1 - September 1983
AB - This paper proposes, as a new LSI reliability estimation method, a procedure for estimating the failure rate of LSI by classifying failures according to failure modes and by expressing the failure rates as functions of the LSI design parameters. As a concrete example, bipolar logic LSIs and MOSRAMs were taken up. Their respective failure modes and the design parameter dependences for the failure rates were considered, in order to obtain the relations between the integration density and the failures. As a result, it was clarified that the failure rate per gate for bipolar logic LSI was inversely proportional to (the number of gates)^0.4 and that the failure rate per bit for MOSRAM was inversely proportional to (the number of bits)^0.7. And it was concluded that the dominant failure modes will be in the metallization for the bipolar logic LSI and in surface degradation for the MOSRAM. Thus, new LSI reliability estimation was carried out. And the technical problems to solve or new technical targets to study in order to improve the reliability of high density LSIs were clarified.
ER -