IEICE TRANSACTIONS on transactions
Paralle Merge Algorithm Suitable for VLSI Implementation
Summary :
A new parallel merge algorithm suitable for VLSI implementation is proposed. This algorithm can merge a given set of sorted sequences in O (N) computation time, where N is a total number of keys in input sequences, and it works on a linear array of simple identical processors.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E67-E No.4 pp.234-235
- Publication Date
- 1984/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- LETTER
- Category
- VLSI Algorithms
Authors
Keyword
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Shin'ichi WAKABAYASHI, Tohru KIKUNO, Noriyoshi YOSHIDA, "Paralle Merge Algorithm Suitable for VLSI Implementation" in IEICE TRANSACTIONS on transactions,
vol. E67-E, no. 4, pp. 234-235, April 1984, doi: .
Abstract: A new parallel merge algorithm suitable for VLSI implementation is proposed. This algorithm can merge a given set of sorted sequences in O (N) computation time, where N is a total number of keys in input sequences, and it works on a linear array of simple identical processors.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e67-e_4_234/_p
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@ARTICLE{e67-e_4_234,
author={Shin'ichi WAKABAYASHI, Tohru KIKUNO, Noriyoshi YOSHIDA, },
journal={IEICE TRANSACTIONS on transactions},
title={Paralle Merge Algorithm Suitable for VLSI Implementation},
year={1984},
volume={E67-E},
number={4},
pages={234-235},
abstract={A new parallel merge algorithm suitable for VLSI implementation is proposed. This algorithm can merge a given set of sorted sequences in O (N) computation time, where N is a total number of keys in input sequences, and it works on a linear array of simple identical processors.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Paralle Merge Algorithm Suitable for VLSI Implementation
T2 - IEICE TRANSACTIONS on transactions
SP - 234
EP - 235
AU - Shin'ichi WAKABAYASHI
AU - Tohru KIKUNO
AU - Noriyoshi YOSHIDA
PY - 1984
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E67-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1984
AB - A new parallel merge algorithm suitable for VLSI implementation is proposed. This algorithm can merge a given set of sorted sequences in O (N) computation time, where N is a total number of keys in input sequences, and it works on a linear array of simple identical processors.
ER -
English
