A 6 NS 16 Bit Parallel Multiplier Using an SST Macrocell Array
Summary :
A 16 bit parallel parallel multiplier is developed by using LCML macrocell circuit design and an improved SST macrocell array with a 0.35 µm emitter width. This multiplier consists of carry-save and carry-lookahead adders. A 6 ns multiplication time is achieved 1.93 W/chip.
- Publication
- IEICE TRANSACTIONS on transactions Vol.E69-E No.4 pp.264-266
- Publication Date
- 1986/04/25
- Publicized
- Online ISSN
- DOI
- Type of Manuscript
- Special Section LETTER (Special Issue: Papers from 1986 National Convention IECE Japan)
- Category
- Silicon Devices and Integrated Circuits
Authors
Keyword
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Masao SUZUKI, Shinsuke KONAKA, "A 6 NS 16 Bit Parallel Multiplier Using an SST Macrocell Array" in IEICE TRANSACTIONS on transactions,
vol. E69-E, no. 4, pp. 264-266, April 1986, doi: .
Abstract: A 16 bit parallel parallel multiplier is developed by using LCML macrocell circuit design and an improved SST macrocell array with a 0.35 µm emitter width. This multiplier consists of carry-save and carry-lookahead adders. A 6 ns multiplication time is achieved 1.93 W/chip.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e69-e_4_264/_p
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@ARTICLE{e69-e_4_264,
author={Masao SUZUKI, Shinsuke KONAKA, },
journal={IEICE TRANSACTIONS on transactions},
title={A 6 NS 16 Bit Parallel Multiplier Using an SST Macrocell Array},
year={1986},
volume={E69-E},
number={4},
pages={264-266},
abstract={A 16 bit parallel parallel multiplier is developed by using LCML macrocell circuit design and an improved SST macrocell array with a 0.35 µm emitter width. This multiplier consists of carry-save and carry-lookahead adders. A 6 ns multiplication time is achieved 1.93 W/chip.},
keywords={},
doi={},
ISSN={},
month={April},}
Copy
TY - JOUR
TI - A 6 NS 16 Bit Parallel Multiplier Using an SST Macrocell Array
T2 - IEICE TRANSACTIONS on transactions
SP - 264
EP - 266
AU - Masao SUZUKI
AU - Shinsuke KONAKA
PY - 1986
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E69-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1986
AB - A 16 bit parallel parallel multiplier is developed by using LCML macrocell circuit design and an improved SST macrocell array with a 0.35 µm emitter width. This multiplier consists of carry-save and carry-lookahead adders. A 6 ns multiplication time is achieved 1.93 W/chip.
ER -
English
