A new gate current model for the AlGaAs/GaAs heterostructure MISFETs is proposed. This model is derived by taking account of the relationship between the surface potential at the hetero-interface and the gate voltage. The new gate current model is shown to be suitable for analyzing logic circuits with heterostructure MISFETs.
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Shuichi FUJITA, Takashi MIZUTANI, "Gate Current Model for Heterostructure MISFETs" in IEICE TRANSACTIONS on transactions,
vol. E69-E, no. 4, pp. 288-290, April 1986, doi: .
Abstract: A new gate current model for the AlGaAs/GaAs heterostructure MISFETs is proposed. This model is derived by taking account of the relationship between the surface potential at the hetero-interface and the gate voltage. The new gate current model is shown to be suitable for analyzing logic circuits with heterostructure MISFETs.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e69-e_4_288/_p
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@ARTICLE{e69-e_4_288,
author={Shuichi FUJITA, Takashi MIZUTANI, },
journal={IEICE TRANSACTIONS on transactions},
title={Gate Current Model for Heterostructure MISFETs},
year={1986},
volume={E69-E},
number={4},
pages={288-290},
abstract={A new gate current model for the AlGaAs/GaAs heterostructure MISFETs is proposed. This model is derived by taking account of the relationship between the surface potential at the hetero-interface and the gate voltage. The new gate current model is shown to be suitable for analyzing logic circuits with heterostructure MISFETs.},
keywords={},
doi={},
ISSN={},
month={April},}
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TY - JOUR
TI - Gate Current Model for Heterostructure MISFETs
T2 - IEICE TRANSACTIONS on transactions
SP - 288
EP - 290
AU - Shuichi FUJITA
AU - Takashi MIZUTANI
PY - 1986
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E69-E
IS - 4
JA - IEICE TRANSACTIONS on transactions
Y1 - April 1986
AB - A new gate current model for the AlGaAs/GaAs heterostructure MISFETs is proposed. This model is derived by taking account of the relationship between the surface potential at the hetero-interface and the gate voltage. The new gate current model is shown to be suitable for analyzing logic circuits with heterostructure MISFETs.
ER -