Relaxation-Based Circuit Simulation
Summary :
A comparison is made for the performance of the relaxation-based circuits simulation algorithms: the iterated timing analysis, the waveform relaxation and the waveform relaxation-Newton, along with the investigation of the following aspects of the convergence properties of these algorithms: (1) variations in their convergence rate with an employed relaxation method, (2) the difference between the speed of convergence of the waveform relaxation and that of the waveform relaxation-Newton, (3) influence of the presence of feedback loops on their convergence rates. In addition the following techniques are surveyed that improve the speed of these algorithms: (1) circuit partitioning, (2) a windowing approach, (3) latency exploitation, (4) iterative stepsize refinement, (5) parallel processing approach.
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- IEICE TRANSACTIONS on transactions Vol.E71-E No.12 pp.1189-1194
- Publication Date
- 1988/12/25
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- REVIEW PAPER
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Kiichi URAHAMA, "Relaxation-Based Circuit Simulation" in IEICE TRANSACTIONS on transactions,
vol. E71-E, no. 12, pp. 1189-1194, December 1988, doi: .
Abstract: A comparison is made for the performance of the relaxation-based circuits simulation algorithms: the iterated timing analysis, the waveform relaxation and the waveform relaxation-Newton, along with the investigation of the following aspects of the convergence properties of these algorithms: (1) variations in their convergence rate with an employed relaxation method, (2) the difference between the speed of convergence of the waveform relaxation and that of the waveform relaxation-Newton, (3) influence of the presence of feedback loops on their convergence rates. In addition the following techniques are surveyed that improve the speed of these algorithms: (1) circuit partitioning, (2) a windowing approach, (3) latency exploitation, (4) iterative stepsize refinement, (5) parallel processing approach.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e71-e_12_1189/_p
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@ARTICLE{e71-e_12_1189,
author={Kiichi URAHAMA, },
journal={IEICE TRANSACTIONS on transactions},
title={Relaxation-Based Circuit Simulation},
year={1988},
volume={E71-E},
number={12},
pages={1189-1194},
abstract={A comparison is made for the performance of the relaxation-based circuits simulation algorithms: the iterated timing analysis, the waveform relaxation and the waveform relaxation-Newton, along with the investigation of the following aspects of the convergence properties of these algorithms: (1) variations in their convergence rate with an employed relaxation method, (2) the difference between the speed of convergence of the waveform relaxation and that of the waveform relaxation-Newton, (3) influence of the presence of feedback loops on their convergence rates. In addition the following techniques are surveyed that improve the speed of these algorithms: (1) circuit partitioning, (2) a windowing approach, (3) latency exploitation, (4) iterative stepsize refinement, (5) parallel processing approach.},
keywords={},
doi={},
ISSN={},
month={December},}
Copy
TY - JOUR
TI - Relaxation-Based Circuit Simulation
T2 - IEICE TRANSACTIONS on transactions
SP - 1189
EP - 1194
AU - Kiichi URAHAMA
PY - 1988
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E71-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1988
AB - A comparison is made for the performance of the relaxation-based circuits simulation algorithms: the iterated timing analysis, the waveform relaxation and the waveform relaxation-Newton, along with the investigation of the following aspects of the convergence properties of these algorithms: (1) variations in their convergence rate with an employed relaxation method, (2) the difference between the speed of convergence of the waveform relaxation and that of the waveform relaxation-Newton, (3) influence of the presence of feedback loops on their convergence rates. In addition the following techniques are surveyed that improve the speed of these algorithms: (1) circuit partitioning, (2) a windowing approach, (3) latency exploitation, (4) iterative stepsize refinement, (5) parallel processing approach.
ER -
English
