To reduce users' load in writing programs for DSPs (Digital Signal Processors), especially those with several pipeline stages, an improved search algorithm is proposed which determines the computational order for a given digital network and generates codes automatically. To search an effective order, a new representation of the precedence form is proposed. A new technique to generate effective codes is also presented. Taking the DSP architecture into account, the method re-allocates the computational order to reduce blanks in the microcodes. These methods are applied to the compilers for µPD77230, µPD7720 and TMS32010/20, which give relatively effective codes.
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Nobuhiko SUGINO, Seiji OHBI, Akinori NISHIHARA, "Computational Ordering of Digital Networks under Pipeline Constraints and Its Application to DSP Compilers" in IEICE TRANSACTIONS on transactions,
vol. E72-E, no. 12, pp. 1299-1306, December 1989, doi: .
Abstract: To reduce users' load in writing programs for DSPs (Digital Signal Processors), especially those with several pipeline stages, an improved search algorithm is proposed which determines the computational order for a given digital network and generates codes automatically. To search an effective order, a new representation of the precedence form is proposed. A new technique to generate effective codes is also presented. Taking the DSP architecture into account, the method re-allocates the computational order to reduce blanks in the microcodes. These methods are applied to the compilers for µPD77230, µPD7720 and TMS32010/20, which give relatively effective codes.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e72-e_12_1299/_p
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@ARTICLE{e72-e_12_1299,
author={Nobuhiko SUGINO, Seiji OHBI, Akinori NISHIHARA, },
journal={IEICE TRANSACTIONS on transactions},
title={Computational Ordering of Digital Networks under Pipeline Constraints and Its Application to DSP Compilers},
year={1989},
volume={E72-E},
number={12},
pages={1299-1306},
abstract={To reduce users' load in writing programs for DSPs (Digital Signal Processors), especially those with several pipeline stages, an improved search algorithm is proposed which determines the computational order for a given digital network and generates codes automatically. To search an effective order, a new representation of the precedence form is proposed. A new technique to generate effective codes is also presented. Taking the DSP architecture into account, the method re-allocates the computational order to reduce blanks in the microcodes. These methods are applied to the compilers for µPD77230, µPD7720 and TMS32010/20, which give relatively effective codes.},
keywords={},
doi={},
ISSN={},
month={December},}
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TY - JOUR
TI - Computational Ordering of Digital Networks under Pipeline Constraints and Its Application to DSP Compilers
T2 - IEICE TRANSACTIONS on transactions
SP - 1299
EP - 1306
AU - Nobuhiko SUGINO
AU - Seiji OHBI
AU - Akinori NISHIHARA
PY - 1989
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E72-E
IS - 12
JA - IEICE TRANSACTIONS on transactions
Y1 - December 1989
AB - To reduce users' load in writing programs for DSPs (Digital Signal Processors), especially those with several pipeline stages, an improved search algorithm is proposed which determines the computational order for a given digital network and generates codes automatically. To search an effective order, a new representation of the precedence form is proposed. A new technique to generate effective codes is also presented. Taking the DSP architecture into account, the method re-allocates the computational order to reduce blanks in the microcodes. These methods are applied to the compilers for µPD77230, µPD7720 and TMS32010/20, which give relatively effective codes.
ER -