A Digital Phase-Locked Loop with a Low Frequency Clock

Hiroomi HIKAWA; Shinsaku MORI

A Digital Phase-Locked Loop with a Low Frequency Clock

Hiroomi HIKAWA, Shinsaku MORI

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Phase-Locked Loops (PLL's) have been playing an important role in communication systems. In recent years efforts have been shifted toward implementation of the PLL's by means of digital circuits and a number of all digital PLL's (DPLL's) have been proposed to solve the problem of stability in the PLL's. One of the major problems of these DPLL's is the requirement of a high frequency local clock for a good phase lock precision, which inevitably makes it difficult to apply the DPLL's into high frequency operations. In this paper, a DPLL which have a good phase lock precision with a low frequency local clock is proposed. A good phase-lock precision is obtained by small phase control quantum, however, it makes the locking range narrow. Then, frequency control is employed to improve the locking range and a binary quantized phase frequency detector is also described. The relation between clock frequency and performances of the system is analyzed and verified by some experiments. Also, analysis and experimental performance are given for both acquisition behavior and steady-state phase error characteristics with white Gaussian noise present, resulting in that a good phase-lock precision and a wide locking range are obtained with a low frequency clock. The experimental results show a very close agreement with the theoretical results.

Publication: IEICE TRANSACTIONS on transactions Vol.E72-E No.2 pp.111-117

Publication Date: 1989/02/25

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Type of Manuscript: PAPER

Category: Communication Device and Circuit

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Hiroomi HIKAWA
Shinsaku MORI

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Hiroomi HIKAWA, Shinsaku MORI, "A Digital Phase-Locked Loop with a Low Frequency Clock" in IEICE TRANSACTIONS on transactions, vol. E72-E, no. 2, pp. 111-117, February 1989, doi: .
Abstract: Phase-Locked Loops (PLL's) have been playing an important role in communication systems. In recent years efforts have been shifted toward implementation of the PLL's by means of digital circuits and a number of all digital PLL's (DPLL's) have been proposed to solve the problem of stability in the PLL's. One of the major problems of these DPLL's is the requirement of a high frequency local clock for a good phase lock precision, which inevitably makes it difficult to apply the DPLL's into high frequency operations. In this paper, a DPLL which have a good phase lock precision with a low frequency local clock is proposed. A good phase-lock precision is obtained by small phase control quantum, however, it makes the locking range narrow. Then, frequency control is employed to improve the locking range and a binary quantized phase frequency detector is also described. The relation between clock frequency and performances of the system is analyzed and verified by some experiments. Also, analysis and experimental performance are given for both acquisition behavior and steady-state phase error characteristics with white Gaussian noise present, resulting in that a good phase-lock precision and a wide locking range are obtained with a low frequency clock. The experimental results show a very close agreement with the theoretical results.
URL: https://global.ieice.org/en_transactions/transactions/10.1587/e72-e_2_111/_p

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@ARTICLE{e72-e_2_111,
author={Hiroomi HIKAWA, Shinsaku MORI, },
journal={IEICE TRANSACTIONS on transactions},
title={A Digital Phase-Locked Loop with a Low Frequency Clock},
year={1989},
volume={E72-E},
number={2},
pages={111-117},
abstract={Phase-Locked Loops (PLL's) have been playing an important role in communication systems. In recent years efforts have been shifted toward implementation of the PLL's by means of digital circuits and a number of all digital PLL's (DPLL's) have been proposed to solve the problem of stability in the PLL's. One of the major problems of these DPLL's is the requirement of a high frequency local clock for a good phase lock precision, which inevitably makes it difficult to apply the DPLL's into high frequency operations. In this paper, a DPLL which have a good phase lock precision with a low frequency local clock is proposed. A good phase-lock precision is obtained by small phase control quantum, however, it makes the locking range narrow. Then, frequency control is employed to improve the locking range and a binary quantized phase frequency detector is also described. The relation between clock frequency and performances of the system is analyzed and verified by some experiments. Also, analysis and experimental performance are given for both acquisition behavior and steady-state phase error characteristics with white Gaussian noise present, resulting in that a good phase-lock precision and a wide locking range are obtained with a low frequency clock. The experimental results show a very close agreement with the theoretical results.},
keywords={},
doi={},
ISSN={},
month={February},}

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TY - JOUR
TI - A Digital Phase-Locked Loop with a Low Frequency Clock
T2 - IEICE TRANSACTIONS on transactions
SP - 111
EP - 117
AU - Hiroomi HIKAWA
AU - Shinsaku MORI
PY - 1989
DO -
JO - IEICE TRANSACTIONS on transactions
SN -
VL - E72-E
IS - 2
JA - IEICE TRANSACTIONS on transactions
Y1 - February 1989
AB - Phase-Locked Loops (PLL's) have been playing an important role in communication systems. In recent years efforts have been shifted toward implementation of the PLL's by means of digital circuits and a number of all digital PLL's (DPLL's) have been proposed to solve the problem of stability in the PLL's. One of the major problems of these DPLL's is the requirement of a high frequency local clock for a good phase lock precision, which inevitably makes it difficult to apply the DPLL's into high frequency operations. In this paper, a DPLL which have a good phase lock precision with a low frequency local clock is proposed. A good phase-lock precision is obtained by small phase control quantum, however, it makes the locking range narrow. Then, frequency control is employed to improve the locking range and a binary quantized phase frequency detector is also described. The relation between clock frequency and performances of the system is analyzed and verified by some experiments. Also, analysis and experimental performance are given for both acquisition behavior and steady-state phase error characteristics with white Gaussian noise present, resulting in that a good phase-lock precision and a wide locking range are obtained with a low frequency clock. The experimental results show a very close agreement with the theoretical results.
ER -