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[Author] Chongxi FENG(3hit)

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  • A Nonlinear Model on the AQM Algorithm GREEN

    Hongwei KONG  Ning GE  Fang RUAN  Chongxi FENG  Pingyi FAN  

     
    PAPER-Packet Transmission

      Vol:
    E86-B No:2
      Page(s):
    622-629

    In this paper, we propose a nonlinear control model to characterize the AQM algorithm-GREEN. Based on this model, we analyze its performance and prove that there exists a stable oscillation when in equilibrium. Furthermore, we also investigate the effects of the factors such as bandwidth, round trip time, and load level on the amplitude and frequency of the oscillation. Theoretical analysis and simulation results indicate that GREEN algorithm is insensitive to the network conditions when the link rate and the round trip time are relatively small and becomes more sensitive to the change of network conditions when the bandwidth delay product is relatively high. For GREEN the adaptability to a wide range of network conditions is based on the compromising of the efficiency.

  • A Scalable Fair Edge-to-Edge Congestion Control Algorithm with Explicit Rate Allocation

    Hongwei KONG  Ning GE  Fang RUAN  Chongxi FENG  Pingyi FAN  

     
    PAPER-Antenna and Propagation

      Vol:
    E86-B No:8
      Page(s):
    2488-2502

    In this paper, we propose a scalable Extended Differentiated-Services (EDS) architecture to guarantee edge-to-edge explicit rate allocation. In presence of flows with explicit rate allocation, to share bandwidth fairly, a new fairness definition is proposed. Based on EDS and the proposed fairness definition, a scalable fair Edge-to-Edge Congestion Control Algorithm with Explicit Rate Allocation (ECC-ERA) is presented to solve the bandwidth assurance problem facing Differentiated Service architecture, where EDS uses congestion control packets to carry the flow-related states and congestion control information. By designing efficiency control and fairness control separately, the ECC-ERA can achieve good scalability to link capacity, round-trip time and number of flows. It will be shown that EDS plus ECC-ERA outperforms the general Diff-Serv bandwidth guarantee approaches. The main advantages of EDS+ECC-ERA are as follows: (1) it not only can guarantee explicit rate allocation, but also can guarantee near-zero packet loss in core routers, high utilization, lower and smoother queueing delay, better fairness and better protection from unresponsive traffic. (2) Neither resource pre-reservation nor sophisticated scheduling mechanisms are required. The simple FIFO at core routers is enough. (3) EDS plus EC-ERA is very efficient and can be used as end-to-end QoS building block.

  • Packet-Mode Scheduling with Proportional Fairness for Input-Queued Switches

    Kang XI  Shin'ichi ARAKAWA  Masayuki MURATA  Ning GE  Chongxi FENG  

     
    PAPER-Switching for Communications

      Vol:
    E88-B No:11
      Page(s):
    4274-4284

    Proportional fair bandwidth allocation in packet switches is a fundamental issue to provide quality of service (QoS) support in IP networks. In input-queued switches, packet-mode scheduling delivers all the segments of a packet contiguously from the input port to the output port, thus greatly simplifying the design of packet reassembly modules and yielding performance advantage over cell-mode scheduling under certain conditions [1]. One of the important issues of packet-mode scheduling is how to achieve fair bandwidth allocation among flows with different packet sizes. This paper presents an algorithm called packet-mode fair scheduling (pFS) that guarantees each flow a bandwidth proportional to its reservation regardless of the packet size distribution and the system load. Simulations show that our approach achieves good fairness as well as high throughput and low packet delay. Compared to algorithms without fairness mechanism, pFS yields significant performance improvement in terms of average packet delay when the traffic is heterogeneous. A hardware implementation is presented to show that the proposed algorithm has low complexity and the computation can be completed in a single clock cycle, which makes pFS applicable to high-speed switches.