A new SOI device structure--a fully DEpleted Lean channel TrAnsistor (DELTA)--which has a new vertical gate structure and an ultra-thin film, bulk Si SOI structure, is proposed. Through experiments and simulation, its fabrication processes and device characteristics are discussed. By using such a new device structure, crystal quality problems caused by recrystallization of poly-Si are solved. DELTA provides a 7.5 times larger channel current than that of conventional planar MOSFETs with the same mask layouts. This is due to a vertical channel structure and a thin film effect. Also, DELTA shows an excellent subthreshold swing of 62 mV/decade. Furthermore, by using a two-carrier device simulator, the punchthrough phenomena in thin film SOI MOSFETs are reexamined from the viewpoint of hole behavior in the substrate. As a result, it was found that the punchthrough resistance of thin film SOI MOSFETs is not always stronger than that of conventional ones. Despite disappearance of the so-called substrate floating effects, attention will still have to be paid to hole behavior in realizing sophisticated SOI devices.

Material representations and algorithms are presented for simulation of nanometer lithography. Organic polymer resists are modeled as collections of overlapping spheres, with each sphere representing a polymer chain. Exposure and post-exposure bake steps are modeled at the nanometer scale for both positive and negative resists. The development algorithm is based on the Poisson removal probability for each sphere in contact with developer. The Poisson removal rate for a given sphere is derived from a mass balance relationship with a macroscopic development rate model. Simulations of electron beam lithography with (poly) methyl methacrylate and Shipley SAL-601 reveal edge roughness standard deviations from 2 to 3 nm, leading to linewidth peak-to-peak 3σ variation of 15 to 22 nm. Typical simulations require about 2 MBytes and under 5 minutes on a Sun Sparc 10/41 engineering workstation.