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[Author] Eiri TAKEDA(1hit)

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  • Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer

    Tsuyoshi IWAGAKI  Eiri TAKEDA  Mineo KANEKO  

     
    PAPER-Logic Synthesis, Test and Verification

      Vol:
    E94-A No:12
      Page(s):
    2563-2570

    This paper proposes a test scheduling method for stuck-at faults in a CHAIN interconnect, which is an asynchronous on-chip interconnect architecture, with scan ability. Special data transfer which is permitted only during test, is exploited to realize a more flexible test schedule than that of a conventional approach. Integer linear programming (ILP) models considering such special data transfer are developed according to the types of modules under test in a CHAIN interconnect. The obtained models are processed by using an ILP solver. This framework can not only obtain optimal test schedules but also easily introduce additional constraints such as a test power budget. Experimental results using benchmark circuits show that the proposed method can reduce test application time compared to that achieved by the conventional method.