IEICE TRANSACTIONS on Fundamentals
Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
Summary :
This paper proposes a test scheduling method for stuck-at faults in a CHAIN interconnect, which is an asynchronous on-chip interconnect architecture, with scan ability. Special data transfer which is permitted only during test, is exploited to realize a more flexible test schedule than that of a conventional approach. Integer linear programming (ILP) models considering such special data transfer are developed according to the types of modules under test in a CHAIN interconnect. The obtained models are processed by using an ILP solver. This framework can not only obtain optimal test schedules but also easily introduce additional constraints such as a test power budget. Experimental results using benchmark circuits show that the proposed method can reduce test application time compared to that achieved by the conventional method.
- Publication
- IEICE TRANSACTIONS on Fundamentals Vol.E94-A No.12 pp.2563-2570
- Publication Date
- 2011/12/01
- Publicized
- Online ISSN
- 1745-1337
- DOI
- 10.1587/transfun.E94.A.2563
- Type of Manuscript
- Special Section PAPER (Special Section on VLSI Design and CAD Algorithms)
- Category
- Logic Synthesis, Test and Verification
Authors
Keyword
Latest Issue
Copyrights notice of machine-translated contents
The copyright of the original papers published on this site belongs to IEICE. Unauthorized use of the original or translated papers is prohibited. See IEICE Provisions on Copyright for details.
Cite this
Copy
Tsuyoshi IWAGAKI, Eiri TAKEDA, Mineo KANEKO, "Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer" in IEICE TRANSACTIONS on Fundamentals,
vol. E94-A, no. 12, pp. 2563-2570, December 2011, doi: 10.1587/transfun.E94.A.2563.
Abstract: This paper proposes a test scheduling method for stuck-at faults in a CHAIN interconnect, which is an asynchronous on-chip interconnect architecture, with scan ability. Special data transfer which is permitted only during test, is exploited to realize a more flexible test schedule than that of a conventional approach. Integer linear programming (ILP) models considering such special data transfer are developed according to the types of modules under test in a CHAIN interconnect. The obtained models are processed by using an ILP solver. This framework can not only obtain optimal test schedules but also easily introduce additional constraints such as a test power budget. Experimental results using benchmark circuits show that the proposed method can reduce test application time compared to that achieved by the conventional method.
URL: https://global.ieice.org/en_transactions/fundamentals/10.1587/transfun.E94.A.2563/_p
Copy
@ARTICLE{e94-a_12_2563,
author={Tsuyoshi IWAGAKI, Eiri TAKEDA, Mineo KANEKO, },
journal={IEICE TRANSACTIONS on Fundamentals},
title={Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer},
year={2011},
volume={E94-A},
number={12},
pages={2563-2570},
abstract={This paper proposes a test scheduling method for stuck-at faults in a CHAIN interconnect, which is an asynchronous on-chip interconnect architecture, with scan ability. Special data transfer which is permitted only during test, is exploited to realize a more flexible test schedule than that of a conventional approach. Integer linear programming (ILP) models considering such special data transfer are developed according to the types of modules under test in a CHAIN interconnect. The obtained models are processed by using an ILP solver. This framework can not only obtain optimal test schedules but also easily introduce additional constraints such as a test power budget. Experimental results using benchmark circuits show that the proposed method can reduce test application time compared to that achieved by the conventional method.},
keywords={},
doi={10.1587/transfun.E94.A.2563},
ISSN={1745-1337},
month={December},}
Copy
TY - JOUR
TI - Flexible Test Scheduling for an Asynchronous On-Chip Interconnect through Special Data Transfer
T2 - IEICE TRANSACTIONS on Fundamentals
SP - 2563
EP - 2570
AU - Tsuyoshi IWAGAKI
AU - Eiri TAKEDA
AU - Mineo KANEKO
PY - 2011
DO - 10.1587/transfun.E94.A.2563
JO - IEICE TRANSACTIONS on Fundamentals
SN - 1745-1337
VL - E94-A
IS - 12
JA - IEICE TRANSACTIONS on Fundamentals
Y1 - December 2011
AB - This paper proposes a test scheduling method for stuck-at faults in a CHAIN interconnect, which is an asynchronous on-chip interconnect architecture, with scan ability. Special data transfer which is permitted only during test, is exploited to realize a more flexible test schedule than that of a conventional approach. Integer linear programming (ILP) models considering such special data transfer are developed according to the types of modules under test in a CHAIN interconnect. The obtained models are processed by using an ILP solver. This framework can not only obtain optimal test schedules but also easily introduce additional constraints such as a test power budget. Experimental results using benchmark circuits show that the proposed method can reduce test application time compared to that achieved by the conventional method.
ER -
English
